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8 - /4 - channel, 24 - bit, simultaneous sampling adc s with power scaling, 110.8 khz bw data sheet ad7768 / ad7768 - 4 rev. a document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is as sumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2016 analog devices, inc. all rights reserved. technical support www.analog.com features precision ac and dc performance 8 - /4 - channel simultaneous sampling 256 ksps maximum adc output data rate per channel 108 db dynamic range 1 10.8 khz maximu m input bandwidth ( ? 3 db bandwidth ) ? 120 db total harmonic distortion ( thd ) typical 2 ppm o f full - scale range (fsr) integral nonlinearity ( inl ) , 50 v offset error, 30 ppm gain erro r optimized power dissipation vs. noise vs. input bandwidth selectable power, speed, and input bandwidth (bw) modes fast: highest speed; 110.8 khz bw, 51.5 mw per c hannel median: half speed, 55.4 khz bw, 27.5 mw per channel eco: lowest power, 1 3.8 khz bw, 9.375 mw per channel input bw range: dc to 1 10.8 khz programmable input bandwidth/sampling rates cyclic redundancy check ( crc ) error checking on data interface dai sy - chaining linear phase digital filter low latency s inc 5 filter wideband brick wall filter: 0.005 db pass - band ripple from dc to 102.4 khz analog i nput p recharge b uffers power supply avdd1 = 5 .0 v, avdd2 = 2 .25 v to 5 .0 v iovdd = 2.5 v to 3.3 v or iovdd = 1.8 v 64- lead lqfp package, no exposed pad temperature range: ?40c to +10 5c applications data acquisition systems: usb/pxi/ethernet instrumentation and i ndustrial c ontrol loop s audio test and measurement vibration and asset condition monitoring 3 - phase power quality analysis sonar high precision medical electroencephalogram ( eeg ) / e lectromyography ( emg ) / electrocardiogram ( ecg ) functional block dia gram adc output data serial interface digital filter engine wideband low ripple filter sinc5 low latency filter spi control interface 1.8v ldo sync_in 1.8v ldo buffered vcm vcm ain1+ ch 1 ain1? ain2+ ch 2 ain2? ain3+ ch 3 ain3? ain4+ ch 4* ain4? ain5+ ch 5* ain5? ain6+ ch 6* ain6? ain7+ ch 7* ain7? ain0+ ch 0 ain0? vcm 8 precharge reference buffers sync_out start reset format1* format0 drdy dclk st0/cs pin/spi st1*/sclk dec0/sdo dec1/sdi avss xtal2/mclk xtal1 mode3/gpio3 to mode0/gpio0 filter/gpio4 - adc - adc - adc - adc - adc - adc - adc - adc dout7* avdd1a, avdd1b dgnd ad7768/ad7768-4 iovdd dregcap regcapa, regcapb avdd2a, avdd2b refx+ refx? offset, gain phase correction offset, gain phase correction offset, gain phase correction offset, gain phase correction offset, gain phase correction offset, gain phase correction offset, gain phase correction offset, gain phase correction dout1 14001-001 dout0 dout2 dout3 dout4 * dout5 * dout6 *, din *these channels/pins exist only on the ad7768. p p p p p p p p p p p p p p p p 16 analog input precharge buffers (p) figure 1 .
ad7768/ad7768 - 4 data sheet rev. a | page 2 of 99 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 3 general description ......................................................................... 5 specifications ..................................................................................... 6 1.8 v iovdd specifications ..................................................... 12 timing specifications ................................................................ 16 1.8 v iovdd timing specifications ....................................... 17 absolute maximum rati ngs .......................................................... 21 thermal resistance .................................................................... 21 esd caution ................................................................................ 21 pin configurations a nd function descriptions ......................... 22 typical performance characteristics ........................................... 30 terminology .................................................................................... 40 theory of operation ...................................................................... 41 clocking, sampling tree, and power scaling ............................. 41 noise performance and resolution .......................................... 42 applications information .............................................................. 44 power supplies ............................................................................ 45 device configuration ................................................................ 46 pin control .................................................................................. 46 spi control .................................................................................. 49 spi control functionality ......................................................... 50 spi control mode extra diagnostic features ........................ 53 circuit information ........................................................................ 54 core signal chain ....................................................................... 54 analog inputs .............................................................................. 55 vcm ............................................................................................. 56 reference input ........................................................................... 56 clock selection ........................................................................... 56 digital filtering ........................................................................... 56 decimation rate control .......................................................... 58 antialiasing ................................................................................. 58 calibration ................................................................................... 59 data interface .................................................................................. 61 setting the format of data output .......................................... 61 adc conversion output: header and data .......................... 62 functionality ................................................................................... 71 gpio functionality .................................................................... 71 ad7768 register map details (spi control) .............................. 72 ad7768 register map ................................................................ 72 channel standby register ......................................................... 74 channel mode a register ......................................................... 74 channel mode b register ......................................................... 75 channel mode select register .................................................. 75 power mode select register ...................................................... 76 general device configuration register .................................. 76 data control: soft reset, sync, and single - shot control register ........................................................................................ 77 interface configuration register .............................................. 78 digital filter ram built in self test (bist) register ............ 78 status register ............................................................................. 79 revision identification register ............................................... 79 gpio control register .............................................................. 79 gpio write data register ......................................................... 80 gpio read data register .......................................................... 80 analog input precharge buffer enable register ch annel 0 to channel 3 .................................................................................... 80 analog input precharge buffer enable register channel 4 to channel 7 .................................................................................... 81 positive reference precharge buf fer enable register ............ 81 negative reference precharge buffer enable register .......... 82 offset registers ........................................................................... 82 gain registers ............................................................................. 83 sync phase offset registers ...................................................... 83 adc diagnostic receive select register ................................ 83 adc diagnostic control register ........................................... 84 modulator delay control register ........................................... 85 chopping control register ....................................................... 85 ad7768 - 4 register map details (spi control) .......................... 86 ad7768 - 4 register map ............................................................ 86 channel standby register ......................................................... 88 channel mode a register ......................................................... 88 channel mode b register ......................................................... 89 channel mode select register .................................................. 89 power mode select register ...................................................... 89 general device configuration register .................................. 90 data control: soft reset, sync, and single - shot control register ........................................................................................ 91 interface configuration re gister .............................................. 91
data sheet ad7768 /ad7768 - 4 rev. a | page 3 of 99 digital filter ram built in self test (bist) register ............ 92 status register .............................................................................. 92 revision identification register ................................................ 93 gpio control register ............................................................... 93 gpio write data register ......................................................... 94 gpio read data register .......................................................... 94 analog input precharge buffer enable register channel 0 and channel 1 ............................................................................. 94 analog input precharge buffer enable register channel 2 and channel 3 ............................................................................. 95 positive reference precharge buffer enable register ............. 95 negative reference precharge buffer enable register ........... 95 offset registers ............................................................................ 96 gain registers .............................................................................. 96 sync phase offset registers ....................................................... 96 adc diagnostic receive select register ................................. 96 adc dia gnostic control register ............................................ 97 modulator delay control register ........................................... 97 chopping control register ........................................................ 98 outline dimensions ........................................................................ 99 ordering guide ........................................................................... 99 revision history 3 /16 rev. 0 to rev. a added ad7768 - 4 ............................................................... universal changed precharge analo g input reference to analog input precharge ........................................................................ throughout changes to general description section ....................................... 5 changes to table 1 ............................................................................ 6 changes to table 2 .......................................................................... 12 changes to tabl e 3 and t 30 parameter, table 4 ............................. 1 6 change s to tabl e 5 .......................................................................... 17 changes to t 30 parameter, table 6 and figure 2 ........................... 18 cha nges to figure 4 and figure 7 .................................................. 19 changes to figure 8 and figure 9 .................................................. 20 chan ges to figure 10 and table 9 ................................................. 22 added figure 11 and table 1 0 ; renumbered sequentially ........ 26 changes to typical perfor mance characteristics section ......... 30 changes to theory of operatio n section and clocking, sampling tr ee, and power scaling section .................................. 41 changes to table 1 1 ........................................................................ 42 added example of power vs. noise performance optimization section and clocking out the adc con v ersion results (dclk) section ............................................................................... 42 changes to applications information s ection and figure 73 ... 4 4 changes to table 1 4 and power sup plies section ....................... 45 moved 1.8 v iovdd operation section ..................................... 46 changes to figure 75, analog supply internal connectivity section, and pin control section .................................................. 46 added figure 76 .............................................................................. 47 cha ng es to channel standby sec tion and accessing the adc register map section ...................................................................... 49 added table 2 2 ................................................................................ 49 changes to channel configuration se ction ................................ 50 change s to channel modes section, reset over spi control interface section, sleep mode section, and channel standby section .............................................................................................. 51 changes to mclk source selection section , interface configuratio n section , and adc synchronization over spi section .............................................................................................. 5 2 added figure 81 .............................................................................. 52 changes to ram built in self test section ................................. 53 changes to analog inputs section and figure 85 ....................... 55 added figure 86 .............................................................................. 55 added table 2 7 ................................................................................ 56 ch anges to vcm section , r eference input section , and digital filtering section .............................................................................. 56 changes to figure 87, figure 88, and figure 89 .......................... 57 changes to antialiasing section and modulator sampling frequency section ........................................................................... 58 changes to modulator chopping frequency section an d table 29 , and modulator saturation point section , .................... 59 changes to sync ph ase offset adjustment section .................... 60 changes to setting the format of data output section ............ 61 added table 32 and figure 93 ....................................................... 61 changes to figure 94 caption and adc conversion out put: header and data section ............................................................... 62 changes to data interface: standard conversion operation section .............................................................................................. 63 changes to figure 99 ...................................................................... 64 added figure 100 ............................................................................ 64 added figure 101 ............................................................................ 65 chan ges to daisy - chaining section and figure 104 .................. 66 added figure 105 ............................................................................ 67 changes to crc ch eck on data in terface section .................... 68 changes to table 35 ........................................................................ 69 changes to table 36 ........................................................................ 70 changes to gpio functionality section and f igure 108 ........... 71 ad ded figure 109 ............................................................................ 71 changes to ad7768 register map details (s pi control) section and table 37 ..................................................................................... 72 changes to cha nnel standby register se ction ........................... 7 4 changes to table 42 and table 4 3 ................................................. 76 changes to table 44 ........................................................................ 77 changes to table 45 and table 46 ................................................. 78 changes to table 49 ........................................................................ 79 changes to table 61 ........................................................................ 8 5 added ad7768 - 4 register map details (spi control) section and table 63 ...................................................................................................... 86
ad7768/ad7768 - 4 data sheet rev. a | page 4 of 99 added table 64 and table 65 ................................................................. 88 a dded tab le 66, table 67, and table 68 ............................................... 89 added table 69 ......................................................................................... 90 added table 70 and table 71 ................................................................. 91 added table 72 and table 73 ................................................................. 92 added table 74 and table 75 ................................................................. 93 added tab le 76, table 77, and table 78 ............................................... 94 added tab le 79, table 80, and table 81 ............................................... 95 added table 82, tab l e 83, table 84, and table 85 .............................. 96 added table 86 and table 87 ................................................................. 97 added table 88 ......................................................................................... 98 changes to ordering guide ................................................................... 99 1/16 revision 0 : initial version
data sheet ad7768 /ad7768 - 4 rev. a | page 5 of 99 general description the ad7768 / ad7768 - 4 are 8 - channel and 4 - channel , simultaneous sampling sigma - delta ( - ) analog - to - digital converter s ( adc s ) , respectively, with a - modulator and digital filter per channel , enabling synchronized sampling of ac and dc signals . the ad7768 / ad7768 - 4 achieve 108 db dynamic range at a maximum input bandwidth of 1 10.8 khz, combined with typical performance of 2 ppm inl , 50 v offset error , and 30 ppm gain error. the ad7768 / ad7768 - 4 user can trade off input bandwidth , output data rate, and power dissipation, and s elect one of three power modes to opt imize for noise targets and power consumption. the flexibility of the ad7768 / ad7768 - 4 allows them to become reusable platform s for low power dc and high performance ac measurement modules. the ad7768 / ad7768 - 4 ha ve three modes : fast m ode (256 ksps maximu m, 110.8 khz input bandwidth, 5 1.5 mw per channel), median mode (128 ksps maxim um, 5 5 .4 khz input bandwidth, 2 7.5 mw per channel) and eco mode (32 ksps maximum, 1 3 .8 khz input bandwidth, 9. 37 5 mw per channel) . the ad7768 / ad7768 - 4 offer extensive digital filtering capabilities, such as a w ideband , low 0.005 db pass - band ripple, antialiasing lo w - pass filter with sharp roll - off , and 105 db stop band attenuation at the nyquist frequency. frequency domain measurements can use th e wideband linear phase filter. this filter has a flat pass band (0.005 db ripple) from dc to 102.4 khz at 256 ksps, from dc to 51.2 khz at 128 ksps, or from dc to 12.8 khz at 32 ksps. the ad7768 / ad7768 - 4 also offer sinc response via a s inc5 f ilter, a low latency path for low bandwidth , and low noise measurements. the w ideband and s inc5 filters can be selected and run on a per channel basis . within these filter options, the user can improve the dynamic range by selecting from decimation rates o f 32, 64, 128, 256, 512, and 1024. the ability to vary the decimation filtering optimizes noise performance to the required input bandwidth. embedded analog functionality on each adc channel makes design easier, such as a p recharge buffer on each an alog input that reduces analog input current and a reference precharge buffer per channel reduces input current and glitches on the reference input terminals. the device operates with a 5 v avdd1 a and avdd1b supply, a 2.25 v to 5.0 v avdd2 a and avdd2b supp ly, and a 2.5 v to 3.3 v or 1.8 v iovdd supply (see the 1.8 v iovdd operation section for specific requirements for operating at 1.8 v iovdd ). the device requires an external reference; the absolute input reference voltage range is 1 v to avdd1 ? avss. for the purposes of clarity within this document, the avdd1a and avdd1b supplies are referred to as avdd1 and the avdd2a and avdd2b supplies are referred to as avdd2. for the negative supplies, avss refer s to the avss1a, avss1b, avss2a, avss2b, and avss pins. the specified operating temperature range is ?40c to +10 5c. the device is housed in a 10 mm 10 mm 64- lead lqfp package with a 12 mm 12 mm printed circuit board (pcb) footprint . t hroughout this data sheet, multifunction pins, such as xtal2 /mclk, are referred to either by the entire pin name or by a single function of the pin, for example mclk, when only that function is relevant.
ad7768/ad7768 - 4 data sheet rev. a | page 6 of 99 specifications avdd 1 a = av dd1b = 4.5 v to 5.5 v, avdd2a = avdd2b = 2.0 v to 5.5 v, iovdd = 2.25 v to 3.6 v, avs s = dgnd = 0 v, refx+ = 4.096 v and refx? = 0 v, mclk = 32.768 mhz, analog input precharge buffers on , reference precharge buffers off , wideband filter, f chop = f mod /32, t a = ? 40c to +105 c , unless otherwise noted. see table 2 for specifications at 1.8 v iovdd. table 1. parameter test conditions/comments min typ max unit adc speed and performance output data rate (odr) , per c hannel 1 fast 8 256 ksps median 4 128 ksps eco 1 32 ksps ?3 db bandwidth fast, w ideba nd f ilter 110.8 khz median, wideband filter 55.4 khz eco, wideband filter 13.8 khz data output coding twos complement, msb first no missing codes 2 24 bits dynamic performance f or 1.8 v operation, see table 2 ; f or dynamic range and snr across all dec - imation rates, see table 12 and table 13 fast decimation by 32, 256 k sps odr dynamic range shorted input, w ideband filter 106.2 108 db signal -to - noise ratio ( snr ) 1 khz, ?0.5 dbfs, sine wave input sinc 5 filter 109 111 db wideband filter 106 107.8 db signal -to - noise - and - distortion ratio ( sinad ) 1 khz, ?0.5 dbfs, sine wave input 104.7 107.5 db tot al harmonic distortion ( thd ) 1 khz, ?0.5 dbfs, sine wave input ? 120 ? 107 db spurious - free dynamic range ( sfdr ) 128 dbc median decimation by 32, 128 khz odr dynamic range shorted input, wideband filter 106.2 108 db snr sinc5 filter , 1 khz, ?0. 5 dbfs, sine wave input 109 111 db wideband filter , 1 khz, ?0.5 dbfs, sine wave input 106 107.8 db sinad 1 khz, ?0.5 dbfs, sine wave input 105. 8 10 7.5 db thd 1 khz, ?0.5 dbfs, sine wave input ?12 0 ?113 db sfdr 128 dbc eco decimation by 32, 32 khz odr dynamic range shorted input, wideband filter 106.2 108 db snr sinc5 filter , 1 khz, ?0.5 dbfs, sine wave input 109 111 db wideband filter , 1 khz, ?0.5 dbfs, sine wave input 106 107.8 db sinad 1 khz, ?0.5 dbfs, sine wave input 105.8 107.5 db thd 1 khz, ?0.5 dbfs, sine wave input ? 120 ?113 db sfdr 128 dbc intermodulaton distortion ( imd ) 3 f a = 9.7 khz, f b = 10.3 khz second order ?125 db third order ?125 db
data sheet ad7768/ad7768 -4 rev. a | page 7 of 99 parameter test conditions/comments min typ max unit accuracy see table 2 for 1.8 v operation inl endpoint method 2 7 p pm of fsr offset error 4 dclk frequency 24 mhz 5 0 115 v 24 m hz to 32.768 mhz dclk f requency 2 7 5 150 v offset error drift dclk f req uency 2 4 mhz 250 nv/c 24 m hz to 32.768 mhz dclk f requency 750 n v/c gain error 4 t a = 25c 3 0 70 p pm of fsr gain drift vs. temperature 2 0.5 1 ppm/c vcm pin output with respect to avss ( avdd1 ? avss )/2 v load regulation (?v out /?i l ) 400 v/ma voltage regulation applies to the following vcm output options only: v cm = ?v out /?(avdd1 ? avss) /2 ; v cm = 1.65 v ; and v cm = 2.5 v 5 v/v short - circuit current 30 ma analog inputs see the analog inputs section differential input voltage range v ref = (ref x +) ? (ref x ?) ?v ref +v ref v input common - mode range 2 av ss a vdd1 v absolute analog input volta ge limits 2 av ss a vdd1 v analog input current fast mode unbuffered differential component 4 8 a/v c ommon - mode component 1 7 a/v precharge buffer on 5 ?20 a input current drift fast mode; se e figure 62 unbuffered 5 n a/v/c precharge buffer on 31 n a/c external reference reference voltage v ref = (ref x +) ? (ref x ?) 1 a vdd1 ? avss v absolute reference voltage limits 2 reference precharge buffers off avss ? 0.05 a vdd1 + 0.05 v av ss a vdd1 v average reference current 7 2 a/v/channel 16 a/v/channel average reference current drift 1 . 7 n a/v/c r e ference precharge buffer on fast mode; see figure 63 re ference prech ar ge buffers off ref e rence precharge buffers on fast mode; see figure 63 re ference precharge buffers off reference pre charge buffers on 4 9 n a/v/c common - mode rejection 95 d b digital filter response low ripple wideband filter filter = 0 decimation rate up to six selectable decimation rates ; s ee the decimation r ate control section 32 1024 group delay latency 34/ odr s ec settling time complete settling , s ee table 35 68/ odr s ec pass - band ripple 2 from dc to 102.4 khz at 256 ksps 0.005 db pass band 0.005 db bandwidth 0.4 odr hz ? 0 .1 db bandwidth 0.40 9 odr hz ?3 db bandwidth 0.433 odr hz stop band frequency attenuation > 105 db 0.49 9 odr hz stop band attenuation see the wideband low ripple filter section 105 db
ad7768/ad7768 - 4 data sheet rev. a | page 8 of 99 parameter test conditions/comments min typ max unit sinc5 fil ter filter = 1 decimation rate up to six selectable decimation rates ; s ee the decimation rate control section 32 1024 group delay latency 3/odr s ec settling time complete settling , s ee table 36 7/odr s ec pass band ?3 db bandwidth 0.204 odr hz rejection ac power supply rejection ratio (psrr) v in = 0.1 v, avdd1 = 5 v, avdd2 = 5 v, iovdd = 2.5 v avdd1 90 db avdd2 100 db iovdd 75 db dc psrr v in = 1 v avdd1 100 db avdd2 118 db iov dd 90 db analog input common - mode rejection ratio (cmrr) dc v in = 0.1 v 95 db ac up to 10 khz 95 db crosstalk ?0.5 dbfs input on adjacent channels ?12 0 db clock crystal frequency 8 32.768 34 mhz external clock (mclk) see the timing specifications section 32.768 mhz duty cycle for data sheet performance 50:50 % mclk pulse width 2 functionality logic low 12.2 ns logic high 12 .2 ns cmos clock input voltage see the l ogic i nputs parameter high, v inh low, v inl lvds clock 2 r l = 100 differential input voltage 100 650 mv common - mode input voltage 800 1575 mv absolute input voltage 1.88 v adc reset 2 adc start - up time after reset 6 time to first drd y , fast mode, decimation by 32 1.58 1.66 ms minimum reset low pulse width t mclk = 1/mclk 2 t mclk logic inputs see table 2 for 1.8 v operation input voltage 2 high, v inh 0.65 iovdd v low, v inl 0.7 v hysteresis 2 0.04 0.09 v leakage current ?10 +0.03 +10 a reset pin 7 ?10 +10 a logic outputs see table 2 for 1.8 v operation output voltage 2 high, v oh i source = 200 a 0.8 iovdd v low, v ol i sink = 400 a 0.4 v
data sheet ad7768 /ad7768 - 4 rev. a | page 9 of 99 parameter test conditions/comments min typ max unit leakage current floating state ?10 +10 a output capacitance floating state 10 pf system calibration 2 full - scale calibration limit 1.05 v ref v zero - scale calibration limit ?1.05 v ref v input span 0.4 v ref 2.1 v ref v power requirements power supply voltage avdd1 ? avss 4.5 5.0 5.5 v avdd2 ? avss 2.0 2.25 to 5.0 5.5 v avss ? dgnd ?2.75 0 v iovdd ? dgnd see table 2 for 1.8 v operation 2.25 2.5 to 3.3 3.6 v power supply currents maximum output data rate, cmos mclk, ei ght doutx signals, all supplies at maximum voltages , all channels in channel mode a except where otherwise sp ecified ad7768 eight c hannels a ctive fast mode avdd1 current reference precharge buffers off/on 36/57.5 40/64 ma avdd2 current 37.5 40 ma iovdd current w ideband filter 63 67 ma sinc5 filter 27 29 ma median mode avdd1 current reference precharge buffers off/on 18.5/29 20.5/32.5 ma avdd2 current 21.3 23 ma iovdd current wideband filter 34 37 ma sinc5 filter 16 18 ma eco mode avdd1 current reference precharge buffers off/on 5.1/8 5.8/9 ma avdd2 current 9.3 10.1 ma iovdd current wideband filter 12.5 13.7 ma si nc5 filter 8 9 ma ad7768 -4 four channels active fast mode avdd1 current reference precharge buffers off/on 18.2/28.8 20.3/32.5 ma avdd2 current 18.8 20.3 ma iovdd cur rent wideband filter 2 43.5 46.8 ma wideband filter, spi mode only; channel mode a set to sinc5 filter 8 37 40 ma sinc5 filter 2 17 18.6 ma median mode a vdd1 current reference precharge buffers off/on 9.3/14.7 10.5/16.6 ma avdd2 current 10.7 11.7 ma iovdd current wideband filter 2 24.4 26.4 ma wideband filter, spi mode only; channel mode a set to sinc5 filter 8 21 23 ma sinc5 filter 2 11 12.3 ma eco mode avdd1 current reference precharge buffers off/on 2.7/4.1 3.1/4.7 ma avdd2 current 4.7 5.3 ma
ad7768/ad7768 - 4 data sheet rev. a | page 10 of 99 parameter test conditions/comments min typ max unit i ovdd current wideband filter 2 10 11.1 ma wideband filter, spi mode only; channel mode a set to sinc5 filter 8 9 10 ma sinc5 filter 2 6.5 7.6 ma ad7768 and ad7768 -4 two channels active 2 serial peripheral interface (spi) control mode only; see the channel standby section f or details on disabling channels fast mode avdd1 current reference precharge buffers off/on 9.3/14.7 10.5/16.6 ma avdd2 current 9.5 10.5 ma iovdd current wideband filter 33.7 36.3 ma wideband filter; disabled channels in channel mode a, and set to sinc5 filter mode 8 23.4 25.5 ma sinc5 filter 11.9 13.3 ma median mode avdd1 current reference precharge buffers off/on 4.8/7.5 5.5/8.6 ma avdd2 current 5.5 6.2 ma iovdd current w ideband filter 19.4 21.1 ma wideband filter; disabled channels in channel mode a, and set to sinc5 filter mode 8 14.1 15.5 ma sinc5 filter 8.5 9.6 ma eco mode avdd1 current reference precharge b uffers off/on 1.52/2.2 1.77/2.6 ma avdd2 current 2.4 3 ma iovdd current wideband filter 8.6 9.7 ma wideband filter; disabled channels in channel mode a, and set to sinc5 filter mode 8 7.2 8 ma sin c5 filter 5.8 6.7 ma standby mode all channels disabled (sinc5 filter enabled) 6.5 8 ma sleep mode 2 full power - down (spi control mode only) 0.73 1.2 ma crystal excitation current extra current in iovdd w hen using an external crystal compared to using the cmos mclk 540 a power dissipation external cmos mclk, all channels active, mclk = 32.768 mhz, all channels in channel mode a except where otherwise specified full operating mode analog precharge buffers on ad7768 wideband filter fast avdd1 = 5 v, avdd2 = iovdd = 2.5 v, reference precharge buffers off 2 412 446 mw avdd1 = 5 v, avdd2 = iovdd = 3.3 v, reference precharge buffers on 2 600 645 mw avdd 1 = 5.5 v, avdd2 = 5.5 v, iovdd = 3.6 v, reference precharge buffers off 631 681 mw median avdd1 = 5 v, avdd2 = iovdd = 2.5 v, reference precharge buffers off 2 220 240 mw avdd1 = 5 v, avdd2 = iovdd = 3.3 v , reference precharge buffers on 2 320 345 mw avdd1 = 5.5 v, avdd2 = 5.5 v, iovdd = 3.6 v, reference precharge buffers off 341 372 mw
data sheet ad7768 /ad7768 - 4 rev. a | page 11 of 99 parameter test conditions/comments min typ max unit eco avdd1 = 5 v, avdd2 = iovdd = 2.5 v, reference precharge buffers off 2 75 85 mw avdd1 = 5 v, avdd2 = iovdd = 3.3 v, reference precharge buffers on 2 107 118 mw avdd1 = 5.5 v, avdd2 = 5.5 v, iovdd = 3.6 v, reference precharge buff ers off 124 137 mw sinc5 filter fast avdd1 = 5 v, avdd2 = iovdd = 2.5 v, reference precharge buffers off 2 325 355 mw avdd1 = 5 v, avdd2 = iovdd = 3.3 v, reference precharge buffers on 2 475 525 mw avdd1 = 5.5 v, avdd2 = 5.5 v, iovdd = 3.6 v, reference precharge buffers off 501 545 mw median avdd1 = 5 v, avdd2 = iovdd = 2.5 v, reference precharge buffers off 2 175 195 mw avdd1 = 5 v, avdd2 = iovdd = 3.3 v, reference precharge buffers on 2 260 285 mw avdd1 = 5.5 v, avdd2 = 5.5 v, iovdd = 3.6 v, reference precharge buffers off 277 304 mw eco avdd1 = 5 v, avdd 2 = iovdd = 2.5 v, reference precharge buffers off 2 65 72 mw avdd1 = 5 v, avdd2 = iovdd = 3.3 v, reference precharge buffers on 2 95 105 mw avdd1 = 5.5 v, avdd 2 = 5.5 v, iovdd = 3.6 v, reference precharge buffers off 108 120 mw ad7768 -4 wideband filter fast avdd1 = 5 v, avdd2 = iovdd = 2.5 v, reference precharge buffers off 235 mw avdd1 = 5 v, avdd2 = iovdd = 3.3 v, reference precharge buffers on 336 mw avdd1 = 5.5 v, avdd2 = 5.5 v, iovdd = 3.6 v, reference precharge buffers off 2 360 392 mw spi mode only; avdd1 = 5.5 v, avdd 2 = 5.5 v, iovdd = 3.6 v, reference precharge buffers off, channel mode a set to sinc5 filter 8 337 368 mw median avdd1 = 5 v, avdd2 = iovdd = 2.5 v, reference precharge buffers off 127 mw avdd1 = 5 v, avd d2 = iovdd = 3.3 v, reference precharge buffers on 181 mw avdd1 = 5.5 v, avdd2 = 5.5 v, iovdd = 3.6 v, reference precharge buffers off 2 198 218 mw spi mode only; avdd1 = 5.5 v, avdd2 = 5.5 v, iovdd = 3.6 v, reference precharge buffers off, channel mode a set to sinc5 filter 8 186 205 mw eco avdd1 = 5 v, avdd2 = iovdd = 2.5 v, reference precharge buffers off 49 mw avdd1 = 5 v, avdd2 = iovdd = 3.3 v, refere nce precharge buffers on 66 mw avdd1 = 5.5 v, avdd2 = 5.5 v, iovdd = 3.6 v, reference precharge buffers off 2 77 87 mw spi mode only; avdd1 = 5.5 v, avdd2 = 5.5 v, iovdd = 3.6 v, reference precharge buffe rs off, channel mode a set to sinc5 filter 8 73 83 mw
ad7768/ad7768 -4 data sheet rev. a | page 12 of 99 parameter test conditions/comments min typ max unit sinc5 filter fast avdd1 = 5 v, avdd2 = iovdd = 2.5 v, reference precharge buffers off 168 mw avdd1 = 5 v, avdd2 = iovdd = 3.3 v, reference precha rge buffers on 248 mw avdd1 = 5.5 v, avdd2 = 5.5 v, iovdd = 3.6 v, reference precharge buffers off 265 291 mw median avdd1 = 5 v, avdd2 = iovdd = 2.5 v, reference precharge buffers off 94 mw avdd1 = 5 v, avdd2 = iovdd = 3.3 v, reference precharge buffers on 137 mw avdd1 = 5.5 v, avdd2 = 5.5 v, iovdd = 3.6 v, reference precharge buffers off 150 167 mw eco avdd1 = 5 v, avdd2 = iovdd = 2.5 v, reference precharge buffers off 40 mw avdd1 = 5 v, avdd2 = iovdd = 3.3 v, reference precharge buffe rs on 55 mw avdd1 = 5.5 v, avdd2 = 5.5 v, iovdd = 3.6 v, reference precharge buffers off 64 74 mw standby mode all channels disabled (sinc5 filter enabled) , avdd1 = 5 v, avdd2 = iovdd = 2.5 v 2 18 mw a vdd1 = 5 v, avdd2 = iovdd = 3.3 v 2 26 mw avdd1 = avdd2 = 5.5 v, iovdd = 3.6 v 29 mw sleep mode 2 full power - down ( spi control mode ), avdd1 = 5 v, avdd2 = iovd d = 2.5 v 1.8 4 mw avdd1 = 5 v, avdd2 = iovdd = 3.3 v 2.5 5 mw avdd1 = avdd2 = 5.5 v, iovdd = 3.6 v 2.7 6.5 mw 1 the output data rate ranges refer to the programmable decimation rates available on the ad7768 / ad7668 -4 fo r a fixe d mclk rate of 32.768 mhz. va rying mclk rates allow users a wider variation of odr. 2 these s pecification s are not production tested but are supported by characterization data at initial product release . 3 see the terminology section for more information abou t the fa and fb input frequencies. 4 following a system zero - scale calibration, the offset error is in the order of the noise for the programmed output data rate selected. a system full - scale calibration reduces the gain error to the order of the noise fo r the programmed output data rate. 5 ?25 a is measured when the analog input is close to either the avdd1 or avss rail. the in put current reduces as the common - mode voltage approaches (avdd1 ? avss)/2. the analog input current scales with the mclk frequency and device power mode. see figure 85 an d figure 86 for more details on how the analog input current scales with input voltage. 6 for lower mclk rates or higher decimatio n rates, use table 35 and table 36 to calculate any additional delay before the first drdy e pulse. 7 the reset e pin has an internal pull - up device t o iovdd. 8 configuring channel mode a t o the sinc5 filter and/or assigning disabled channels to channel mode a allows a lower power consumption to be achieved. to do this , the user must be operating in spi control mode because it requires assigning channels to different channel modes (only poss ible in spi control mode). if using pin control mode , all channels , whether active or in standby , are assigned to the same channel group and use the same filter type. this means that , in pin control mode , a higher current consumption is seen from disabled channels than can be achieved in spi mode. see the channel modes section for more details. 1.8 v iovdd specifications avdd1a = avdd1b = 4.5 v to 5.5 v, avdd2a = avdd2b = 2.0 v to 5.5 v, iovdd = 1.72 v to 1.88 v, avss = dgnd = 0 v, refx+ = 4.096 v and refx? = 0 v, mclk = 32.76 8 mhz, analog precharge buffers on, reference precharge buffers off, wideband filter, f chop = f mod /32, t a = ? 40c to +105 c , unless otherwise noted. table 2. parameter test condit ions/comments min typ max unit dynamic performance for dynamic range and snr across all decimation rates, see table 12 and table 13 fast decimation by 32, 256 ksps o dr dynamic range shorted input, wideband filter 106.2 108 db snr sinc5 filter , 1 khz, ?0.5 dbfs, sine wave input 109 111 db wideband filter , 1 khz, ?0.5 dbfs, sine wave input 106 107.8 db
data sheet ad7768 /ad7768 - 4 rev. a | page 13 of 99 parameter test condit ions/comments min typ max unit sinad 1 1 khz, ?0.5 dbfs, sine wave input 103.8 107.5 db thd 1 khz, ?0.5 dbfs, sine wave input ?1 20 ?107 db sfdr 128 dbc median decimat ion by 32, 128 khz odr dynamic range shorted input, wideband filter 106.2 108 db snr 1 khz, ?0.5 dbfs, sine wave input sinc5 filter 109 111 db wideband filter 106 107.8 db sinad 1 khz, ?0.5 dbfs, sine wave input 105.8 107.5 db thd 1 kh z, ?0.5 dbfs, sine wave input ?120 ?113 db sfdr 128 dbc eco decimation by 32, 32 khz odr dynamic range shorted input, wideband filter 106.2 108 db snr sinc5 filter , 1 khz, ?0.5 dbfs, sine wave input 109 111 db wideband filter , 1 khz, ?0.5 dbfs, sine wave input 106 107.8 db sinad 1 khz, ?0.5 dbfs, sine wave input 105.8 107.5 db thd 1 khz, ?0.5 dbfs, sine wave input ?120 ?113 db sfdr 128 dbc accuracy 1 inl endpoint method 2 7 ppm of fsr offset error 2 dclk frequency 24 mhz 50 115 v 24 mhz to 32.768 mhz dclk frequency 75 170 v offset error drift dclk frequency 24 mhz 250 nv/c 24 mhz to 32.768 mhz dclk frequency 750 nv/c gain error 2 t a = 25c 60 120 ppm/fsr gain drift vs. temperature 0.5 2 ppm/c logic inputs input voltage 1 high, v inh 0.65 iovdd v low, v inl 0.4 v hysteresis 1 0.04 0.2 v leakage current ?10 + 0.03 +10 a reset pin ?10 +10 a logic outputs output voltage 1 high, v oh i source = 200 a 0.8 iovdd v low, v ol i sink = 400 a 0.4 v leakage current floating state ?10 +10 a output capacitance floating state 10 pf power requirements power supply voltage avdd1 ? avss 4.5 5.0 5.5 v avdd2 ? avss 2.0 2.25 to 5.0 5.5 v avss ? dgnd ?2.75 0 v iovdd ? dgnd dregcap shorted to iovdd 1.72 1.8 1.88 v power supply currents 1 maximum output data rate, cmos mclk, eight doutx signals, all supplies at maxi mum voltages, all channels in channel mode a except where otherwise specified ad7768 eight c hannels a ctive fast mode avdd1 current reference precharge buffers off/on 36/57.5 40/64 ma avdd2 current 37.5 40 ma
ad7768/ad7768 - 4 data sheet rev. a | page 14 of 99 parameter test condit ions/comments min typ max unit iovdd current wideband filter 63 69 ma sinc5 filter 26 28.4 ma median mode avdd1 current reference precharge buffers off/on 18.5/29 20.5/32.5 ma avdd2 current 21.3 23 ma iovdd current wideband filter 34 36.8 ma sinc5 filter 15 16.8 ma eco mode avdd1 current reference precharge buffers off/on 5.1/8 5.8/9 ma avdd2 current 9.3 10.1 ma iovdd current wideband filter 11.6 12.9 ma sinc5 filter 7 8.1 m a ad7768 -4 four c hannels a ctive fast mode avdd1 current reference precharge buffers off/on 18.2/28.8 20.3/32.5 ma avdd2 current 18.8 20.3 ma iovdd current wideband fil ter 43.9 47.7 ma w ideband filter, spi mode only; channel mode a set to sinc5 filter 3 36.8 41 ma sinc5 filter 16 17.7 ma median mode avdd1 current reference precharge buffers off/on 9.3/14.7 10.5/16.6 ma avdd2 current 10.7 11.7 ma iovdd current wideband filter 24 26.1 ma wideband filter, spi mode only; channel mode a set to sinc5 filter 3 20.4 22.7 ma sinc5 filter 10 11.3 ma eco mode avdd1 current reference precharge buffers off/ on 2.7/4.1 3.1/4.7 ma avdd2 current 4.7 5.3 ma iovdd current wideband filter 9 10.2 ma wideband filter, spi mode only; channel mode a set to sinc5 filter 3 8.1 9.2 ma sinc5 filter 5.5 6.5 ma ad7768 and ad7768 -4 two channels active spi control mode only; see the channel standby section for details on disabling channels fast mode avdd1 current reference precharge buffers off/on 9.3/14.7 1 0.5/16.6 ma avdd2 current 9.5 10.5 ma iovdd current wideband filter 33.8 36.7 ma wideband filter, spi mode only; disabled channels in channel mode a, and set to sinc5 filter 3 23.1 25.6 ma sinc5 filte r 11 12.3 ma median mode avdd1 current reference precharge buffers off/on 4.8/7.5 5.5/8.6 ma avdd2 current 5.5 6.2 ma iovdd current wideband filter 18.9 20.6 ma w ideband filter, spi mode only; disabled channels in channel mode a, and set t o sinc5 filter 3 13.4 15.1 ma sinc5 filter 7.4 8.6 ma eco mode avdd1 current reference precharge buffers off/on 1.52/2.2 1.77/2.6 ma avdd2 current 2.4 3 ma
data sheet ad7768/ad7768 -4 rev. a | page 15 of 99 parameter test condit ions/comments min typ max unit iovdd current wideband filter 7.6 8.8 ma w ideband filter, spi mode only; disabled channels in channel mode a, and set to sinc5 filter 3 6.3 7.2 ma sinc5 filter 4.8 5.8 ma standby mode all channels disabled (sinc5 filter enabled) 6.5 8 ma sleep mode full power - down ( spi control mode ) 0.73 1.2 ma crystal excitation current extra current in iovdd when using an external crystal compared to using the cmos mclk 540 a power dissipation 1 exter nal cmos mclk, all channels active, avdd1 = avdd2 = 5.5 v, iovdd = 1.88 v, mclk = 32.768 mhz, all channels in channel mode a except where otherwise noted full operating mode analog precharge buffers on ad7768 eight channels active wideband filter fast reference precharge buffers off 524 571 mw reference precharge buffers on 638 704 mw median reference prech arge buffers off 284 309 mw reference precharge buffers on 342 375 mw eco reference precharge buffers off 98.5 109 mw reference precharge buffers on 118 130 mw sinc5 filter fast reference precharge buffers off 455 495 mw median reference precharge buffers off 248 271 mw eco reference precharge buffers off 94 105 mw ad7768-4 four channels active wideband filter fast reference precharge buffers off 287 314 mw reference precharge buffers on 345 381 mw median reference precharge buffers off 156 172 mw reference precharge buffers on 185 206 mw eco reference precharge buffers off 58 66 mw reference precharge buffers on 66 75 mw sinc5 filter fast reference precharge buffers off 234 257 mw median reference precharge buffers off 129 144 mw eco reference precharge buffers off 51 59 mw standby mode all channels disabled (sinc5 filter enabled) 17 mw sleep mode full power - down ( spi control mode ) 1.5 4.5 mw 1 these s pecifications are not production tested but are supported by characterization data at initial product release . 2 f ollowing a system zero - scale calibration, the offset error is in the order of the noise for the programmed output data rate selected. a system full - scale calibration r educes the gain error to the order of the noise for the programmed output data rate. 3 th is configuration of setting channel mode a to the sinc5 filter and/or assigning disabled channels to channel mode a allows a lower power consumption to be achieved due to the disabling of internal clocks on the disabled only and sinc5 only channel modes. t his configuration requires assigning sinc5 and wideband filters to different channels, or channel modes, and is only available in spi control mode. in pin control mode, all channels, whether active or in standby, effectively use the same channel mode. see the channel modes section for more details.
ad7768/ad7768 - 4 data sheet rev. a | page 16 of 99 timing specification s avdd1a = av dd1b = 5 v, avdd2a = avdd2b = 5 v, iovdd = 2.25 v to 3.6 v, input logic 0 = dgnd, input logic 1 = iovdd; c load = 10 pf on the dclk pin, c load = 20 pf on the other digital outputs; refx+ = 4.096 v, t a = ? 40c to +105 c . see table 5 and table 6 for timing specifications at 1.8 v iovdd. table 3. data interface timing 1 parameter description test cond itions/comments min typ max unit mclk m aster c lock 1.15 34 mhz f mod modulator f requency fast m ode mclk/4 hz median m ode mclk/8 hz eco m ode mclk/32 hz t 1 drdy high time t dclk = t 8 + t 9 t dclk ? 10% 28 ns t 2 dclk rising ed ge to drdy rising edge 2 ns t 3 dclk rising to drdy falling ? 3.5 0 ns t 4 dclk rise to doutx valid 1.5 ns t 5 dclk rise to doutx invalid ?3 ns t 6 doutx valid to dclk falling 9.5 t dclk /2 ns t 7 dclk falling edge to doutx invalid 9.5 t dclk /2 ns t 8 dclk high time, dclk = mclk/1 50:50 cmos clock t dclk /2 t dclk /2 (t dclk /2) + 5 ns t 8a = dclk = mclk/2 t mclk = 1/mclk t mclk ns t 8b = dclk = mclk/4 2 t mclk ns t 8c = dclk = mclk/8 4 t mclk ns t 9 dclk low time dclk = mclk/1 50:50 cmos clock (t dclk /2) ? 5 t mclk /2 t dclk /2 ns t 9a = dclk = mclk/2 t mclk ns t 9b = dclk = mclk/4 2 t mclk ns t 9c = dclk = mclk/8 4 t mclk ns t 10 mclk rising to dclk rising cmos clock 30 ns t 11 setup time ( daisy - chain inputs) dout6 and dout7 on the ad7768 , din on the ad7768 -4 14 ns t 12 hold time ( daisy - chain inputs) dout6 and dout7 on the ad7768 , din on the ad7768 -4 0 ns t 13 start low time 1 t mclk ns t 14 mclk to sync_out valid cmos clock sync_out retime_en bit disabled ; measured from falling edge of mclk 4.5 22 ns sync_out retime_en bit enabled ; measured from rising edge of mclk 9.5 27.5 ns t 15 sync_in setup time cmos clock 0 n s t 16 sync_in hold time cmos clock 10 ns 1 these s pecification s are not production tested but are supported by characterization data at initial product release . table 4 . spi control interface timing 1 parameter description test conditions/comments min typ max unit t 17 sclk period 100 ns t 18 cs falling edge to sclk rising edge 26.5 ns t 19 sclk falling edge to cs rising edge 27 ns t 20 cs falling edge to data output enable 22.5 40.5 ns t 21 sclk high time 20 50 ns t 22 sclk low time 20 50 ns t 23 sclk falling e dge to sdo valid 15 ns t 24 sdo hold time after sclk falling 7 ns t 25 sdi setup time 0 ns t 26 sdi hold time 6 ns t 27 sclk enable time 0 ns
data sheet ad7768 /ad7768 - 4 rev. a | page 17 of 99 parameter description test conditions/comments min typ max unit t 28 sclk disable time 0 ns t 29 cs high time 10 ns t 30 cs low time f mod = mclk/4 1.1 t mclk ns f mod = mclk/8 2.2 t mclk ns f mod = mclk/32 8.8 t mclk ns 1 these s pecifications are not production tested but are supported by characterization data at initial product release . 1.8 v iovdd timing s pecifications avdd1a = avdd1b = 5 v, avdd2a = avdd2b = 5 v, iovdd = 1.72 v to 1.88 v (dregcap tied to iovdd), input logic 0 = dgnd, input logic 1 = iovdd, c l oad = 10 pf on dclk pin, c load = 20 pf on other digital outputs, t a = ?40c to +105 c. t odr is 1/odr. table 5 . data interface timing 1 parameter description test conditions/comments min typ max un it mclk master c lock 1.15 34 mhz f mod modulator f requency fast m ode mclk/4 hz median m ode mclk/8 hz eco m ode mclk/32 hz t 1 drdy high time t dclk ? 10% 28 ns t 2 dclk rising edge to drdy rising edge 2 ns t 3 dclk rising to drdy falling ? 4.5 0 ns t 4 dclk rise to doutx valid 2.0 ns t 5 dclk rise to doutx invalid ? 4 ns t 6 doutx valid to dclk falling 8.5 t dclk /2 ns t 7 dclk falling edge to doutx invalid 8.5 t dclk /2 ns t 8 dc lk high time, dclk = mclk/1 50:50 cmos clock t dclk /2 t dclk /2 (t dclk /2) + 5 ns t 8a = dclk = mclk/2 t mclk ns t 8b = dclk = mclk/4 2 t mclk ns t 8c = dclk = mclk/8 4 t mclk ns t 9 dclk low time dclk=mclk/1 50:50 cmos clock (t dclk /2) ? 5 t mclk /2 ( t dclk /2 ns t 9a = dclk = mclk/2 t mclk ns t 9b = dclk = mclk/4 2 t mclk ns t 9c = dclk = mclk/8 4 t mclk ns t 10 mclk rising to dclk rising cmos clock 37 ns t 11 setup time (daisy - chain inputs) dout6 and dout7 on the ad7768 , din on the ad7768 -4 14 ns t 12 hold time (daisy - chain inputs) dout6 and dout7 on the ad7768 , din on the ad7768 -4 0 ns t 13 start low time 1 t mclk ns t 14 mclk to sync_out valid cmos clock sync_out retime_en bit disabled ; measured from falling edge of mclk 10 31 ns sync_out retime_en bit enabled ; measured from rising edge of mclk 15 37 ns t 15 sync_in setup time cmos clock 0 ns t 16 sync_in hold time cmos clock 11 ns 1 these s pecification s are not production tes ted but are supported by characterization data at initial product release .
ad7768/ad7768 - 4 data sheet rev. a | page 18 of 99 table 6 . spi control interfac e timing 1 parameter description test conditions/comments min typ max unit t 17 sclk period 100 ns t 18 cs falling edge to sclk risi ng edge 31.5 ns t 19 sclk falling edge to cs rising edge 30 ns t 20 cs falling edge to data output enable 29 54 ns t 21 sclk high time 20 50 ns t 22 sclk low time 20 50 ns t 23 sclk falling edge to sdo valid 16 ns t 24 sdo hold time after sclk falling 7 ns t 25 sdi setup time 0 ns t 26 sdi hold time 10 ns t 27 sclk enable time 0 ns t 28 sclk disable time 0 ns t 29 cs high time 10 ns t 30 cs low time f mod = mclk/4 1.1 t mclk ns f mod = mclk/8 2.2 t mclk ns f mod = mclk/32 8.8 t mclk ns 1 these s pecification s are not production tes ted but are supported by characteriza tion data at initial product release . timing diagrams drd y dclk lsb lsb msb doutx t 1 t odr t 7 t 6 t 5 t 4 t 3 t 2 t 8 t 9 14001-002 figure 2 . data interface timing diagram t 8a t 8b t 9a mclk dclk = mclk/2 dclk = mclk/4 dclk = mclk/8 t 10 t 9b t 8c t 9c 14001-003 figure 3 . mclk to dclk divider timing diagram
data sheet ad7768/ad7768-4 rev. a | page 19 of 99 t 11 t odr t 12 drdy dclk dout6 and dout7 14001-004 figure 4. daisy-chain setup and hold timing diagram t 13 t 14 mclk start s ync_out 14001-005 figure 5. asynchronous start and sync_out timing diagram t 16 t 15 mclk sync_in t 15 14001-006 figure 6. synchronous sync_in e pulse timing diagram cs s clk sdo msb t 18 t 17 t 21 t 30 t 22 t 23 t 24 t 20 t 19 14001-007 figure 7. spi serial read timing diagram
ad7768/ad7768 - 4 data sheet rev. a | page 20 of 99 cs sclk sdi msb lsb t 18 t 25 t 26 14001-008 t 30 figure 8 . spi serial write timing diagram cs sclk t 28 t 29 t 27 14001-009 figure 9 . sclk enable and disable timing diag ram
data sheet ad7768 /ad7768 - 4 rev. a | page 21 of 99 absolute maximum rat ings table 7. parameter rating avdd1, avdd2 to avss 1 ?0.3 v to +6.5 v avdd1 to dgnd ?0.3 v to +6.5 v iovdd to dgnd 0.3 v to + 6. 5 v iovdd, dregcap to dgnd (iovdd t ied to dregcap for 1.8 v o peration ) 0.3 v to +2.25 v iovdd to avss 0.3 v to +7.5 v avss to dgnd 3.25 v to +0.3 v analog input voltage to avss ? 0.3 v to avdd1 + 0.3 v reference input voltage to avss ? 0.3 v to avdd1 + 0.3 v digital input voltage to dgnd ?0.3 v to iovdd + 0.3 v digital output voltage to dgnd ?0.3 v to iovdd + 0.3 v operating temperature range ?40c to +105c sto rage temperature range ?65c to +150c pb - free temperature, soldering reflow (10 sec to 30 sec) 260 c maximum junction temperature 150c maximum package classification temperature 260c 1 transient currents of up to 100 ma do not cause scr latch - u p. stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational sect ion of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. thermal resistance ja is specified for the worst case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 8 . thermal resistance package type ja jc unit jedec board layers 64- lead lqfp 38 9.2 c/w 2p2s 1 1 2 p2s is a jedec standard pcb configuration per jedec standard jesd51 - 7. esd caution
ad7768/ad7768 - 4 data sheet rev. a | page 22 of 99 pin configuration s and function descrip tions 64 ain0+ 63 ain0? 62 avss2a 61 regcapa 60 avdd2a 59 vcm 58 clk_sel 57 pin/spi 56 format0 55 format1 54 avss 53 avdd2b 52 regcapb 51 avss2b 50 ain4? 49 ain4+ 47 ain5+ 46 avss1b 45 avdd1b 42 ain6? 43 ref2+ 44 ref2? 48 ain5? 41 ain6+ 40 ain7? 39 ain7+ 37 start 36 sync_in 35 iovdd 34 dregcap 33 dgnd 38 sync_out 2 ain1+ 3 avss1a 4 avdd1a 7 ain2? 6 ref1+ 5 ref1? 1 ain1? 8 ain2+ 9 ain3? 10 ain3+ 12 mode0/gpio0 13 mode1/gpio1 14 mode2/gpio2 15 mode3/gpio3 16 st0/cs 1 1 filter/gpio4 17 st1/sclk 18 dec1/sdi 19 dec0/sdo 20 dout7 21 dout6 22 dout5 23 dout4 24 dout3 25 dout2 26 dout1 27 dout0 28 dclk 29 drdy 30 reset 31 xtal1 32 xtal2/mclk ad7768 top view (not to scale) 14001-010 analog inputs and outputs decoupling capacitor pins supply and ground pins digital pins figure 10 . ad7768 pin c onfiguration table 9 . pin function descriptions pin no. mnemonic type 1 description 1 ain1? ai negative analog input to adc channel 1. 2 ain1+ ai positive analog input to adc channel 1. 3 avss1a p negative analog supply. this pin is n ominally 0 v. 4 avdd1a p analog supply voltage , 5 v 10% with r espect to avss. 5 ref1? ai reference input , negative. ref1 ? is the negative reference terminal for channel 0 to channel 3. the ref1? voltage range is from avss to (avdd1 ? 1 v). decouple this pin to avss with a high quality capacitor, and maintain a low impedance between this capacitor and pin 3. 6 ref1+ ai reference input , positive. ref1+ is the positive reference terminal for channel 0 to channel 3. the ref1+ voltage range is from (avs s + 1 v) to avdd1. apply an external differential reference voltage between ref1+ and ref1? in the range from 1 v to |avdd1 ? avss |. decouple this pin to avss with a high quality capacitor, and maintain a low impedance between this capacitor and pin 3. 7 ain2? ai negative analog input to adc channel 2. 8 ain2+ ai positiv e analog input to adc channel 2. 9 ain3? ai negative analog input to adc channel 3. 10 ain3+ ai positive analog input to adc channel 3. 11 filter/gpio4 di/o filter select/general - purpose input / output 4 . in pin control mode , this pin selects the filter type. set this pin to logic 1 for the sinc5 filter. this sinc5 filter is a low latency filter, and is best for dc applications or wh ere a user has specialized post filtering implemented off chip. set this pin to logic 0 for the wideband low ripple filter response. this filter has a steep transition band and 105 db stop band attenuation. full attenuation at nyquist (odr/2) means that no aliasing occurs at odr/2 out to the first chopping zone. when in spi control mode, this pin can be used as a ge neral - purpose input/output (gpio4). see table 49 for more details.
data sheet ad7768 /ad7768 - 4 rev. a | page 23 of 99 pin no. mnemonic type 1 description 12, 13, 14, 15 mode0/gpio0, mode1/gpio1, mode2/gpio2, mode3/gpio3 di/di/o mode selection/general - purpose input/output pin 0 to pin 3 . in pi n control mode, the modex pins set the mode of operation for all adc channels, controlling power consumption, dclk frequency, and the adc conversion type, allowing one - shot conversion operation. in spi control mode, the gpiox pins, in addition to the f ilter /gpio4 pin, form five general - purpose input/output pins (gpio4 to gpio0). see table 49 for more details. 16 st0/ cs di standby 0/chip select input. in pin control mode, a logic 1 places channel 0 to channel 3 into standby mode. in spi control mode, this pin is the active low chip select input to the spi control interface. the vcm voltage output is associated with the channel 0 circuitry. if channel 0 is put into standby mode, the vcm voltage output is also di sabled for maximum power saving s . channel 0 must be enabled while vcm is being used externally to the ad7768 . 17 st1/sclk di standby 1/serial clock input. in pin control mode, a logic 1 on this pin places channel 4 to channel 7 into standby mode. in spi control mode, this pin is the serial clock input pin for the spi control interface. the crystal excitation circuitry is associated with the channel 4 circu itry. if channel 4 is put into standby mode, the crystal circuitry is also disabled for maximum power savings. channel 4 must be enabled while the external crystal is used on the ad7768 . 18 dec1/sdi di decimation rate control input 1/serial data input. in pin control mode, the dec0 and dec1 pins configure the decimation rate for all adc channels. see table 17 in the setting the decimation rate section for more information . in spi control mode, this pin is the serial data input pin used to write data to the ad7768 register bank. 19 dec0/sdo di/o decimation rate control input 0/serial data output. in pin control mode, the dec0 and dec1 pins configure the decimation rate for all adc channels. see table 17 in the setting the decimation rate section for more information . in spi control mode, this pin is the serial data output pin, allowing readback from the ad7768 registers. 20 d out7 di/o conversion data output 7. this pin is synchronous to dclk and framed by drdy . this pin acts as a digital input from a separate ad7768 device if configured in a synchronized multidevice daisy chain when the formatx pins are configured as 01. to use the ad7768 in a daisy chain, hardwire the formatx pins as 01, 10, or 11, depending on the best interfacing format for the applicati on. when formatx is set to 01, 10, or 11 , and daisy - chaining is not used, connect this pin to gro und through a pull - down resistor. 21 dout6 di/o conversion data output 6. this pin is synchronous to dclk and framed by drdy . this pin acts as a digital input from a separate ad7768 device if configured in a synchronized multidevice daisy chain. to use this pin in a daisy chain, hardwire the formatx pins as 01, 10, or 11, depending on the best interfacing format for the application. when formatx is set to 01, 10 , or 11, and daisy chaining is not used, connect this pin to ground through a pull - down resistor. 22 dout5 do conversion data output 5. this pin is synchronous to dclk and framed by drdy . 23 dout4 do conversion data output 4. this pin is synchro nous to dclk and framed by drdy . 24 dout3 do conversion data output 3. this pin is synchronous to dclk and framed by drdy . 25 dout2 do conversion data output 2. this pin is synchronous to dclk and framed by drdy . 26 dout1 do conversion data output 1. this pin is synchronous to dclk and framed by drdy . 27 dout0 do conversion data output 0. this pin is synchronous to dclk and framed by drdy 28 dclk do adc conversion data clock. this pin clocks conversion data out to the digital host ( digital signal processor ( dsp ) / field - programmable gate array ( fpga ) ). this pin is synchronous with drdy and any conversion data output on dout0 to dout7 and is derived from the mclk signal. this pin is unrelated to the control spi interface. 29 drdy do data ready. drdy is a p eriodic signal output framing the conversion results from the eight adcs. this pin is synchronous to dclk and d out0 to dout7. 30 reset di hardware asynchronous reset input. after the device is fully powered up, it is recommended to perform a hard reset using this pin or, alternatively, to perform a soft reset by issuing a reset over the spi cont rol interface
ad7768/ad7768 - 4 data sheet rev. a | page 24 of 99 pin no. mnemonic type 1 description 31 xtal1 di input 1 for crystal or connection to an lvds clock. when clk_sel is 0, connect xtal1 to dgnd. the crystal excitation circuitry is associated with the channel 4 circuitry. if channel 4 is put into standby mode, the crystal circuit ry is also disabled for maximum power savings. channel 4 must be enabled while the external crystal is used on the ad7768 . when used with an lvds clock, connect this pin to one trace of th e lvds signal pair. when used as an lvds input, a rising edge on this pin is detected as a rising mclk edge by the ad7768 . 32 xtal2/mclk di input 2 for cmos or crystal/lvds sampling clock . see the clk_sel pin for the details of this configuration. external crystal: xtal2 is connected to the external crystal. lvds clock : w hen used with an lvds clock, connect this pin to the second trace of the lvds signal pair. cmos clock: thi s pin operates as an mclk input. this pin is a cmos input with a logic level of iovdd/dgnd. when used as a cmos clock input, a rising edge on this pin is detected as a rising mclk edge by the a d7768 . the crystal excitation circuitry is associated with the channel 4 circuitry. if channel 4 is put into standby mode, the crystal circuitry is also disabled for maximum power savings. channel 4 must be enabled while the external crystal is us ed on the ad7768 . 33 dgnd p digital ground. this pin is nominally 0 v. 34 dregcap ao digital low dropout ( ldo ) regulator output. decouple this pin to dgnd with a high quality, low esr, 1 0 f capacitor. for optimum performance, use a decoupling capacitor with an esr specification of less than 400 m . this pin is not for use in circuits external to the ad7768 . for 1.8 v iovdd operation, connect this p in to iovdd via an external trace to provide power to the digital processing c ore. 35 iovdd p digital supply. this pin sets the logic levels for all interface pins. iovdd also powers the digital processing core via the digital ldo when iovdd is at least 2.25 v . for 1.8 v iovdd operation, connect this pin to d regcap via an external trace to provide power to the digital processing core. 36 sync_in di synchronization input. sync_in receives the synchronous signal from sync_out . it is used in the synchronization of any ad7768 that requires simultaneous sampling or is in a daisy chain. i gnore the start and sync_out function s if the sync_in pin is connected to the s ystem synchronization pulse. this signal pulse must be synchronous to the mclk clock domain. in a daisy - chained system of ad7768 devices, two successive synchronization pulses must be appl ied to guarantee that all adcs are synchronized. two synchronization pulses are also required in a system of more than one ad7768 device sharing a single mclk signal, where the drdy pin of only one device is used to detect new data. 37 start di start signal. the st art pulse synchronize s the ad7768 to other devices. the signal can be asynchronous. the ad7768 samples the input and then outputs a sync_out pulse. this sync_out pulse must be routed to the sync_in pin of this device, and any other ad7768 devices that must be synchronized together. this means that the user does not need to run the adcs and their digital host from the same clock domain , which is u seful when there are long traces or back planes between the adc and the controller. if this pin is not used , it must be tied to a l ogic 1 through a pull - up resistor. in a daisy - chained system of ad7768 devices, two successive synchronization pulses must be applied to guarantee that all adcs are synchronized. two synchronization pulses are also required in a system of more than one ad7768 device sharing a single mclk signal, where the drdy pin of only one device is used to detect new data. 38 sync_out do synchronization output. this pin operates only when the start input is used. when using the start input feature, the sync_out pin must be co nnected to sync_in via an external trace. sync_out is a digital output that is synchronous to the mclk signal; the synchronization signal driven in on start is internally synchronized to the mclk signal and is driven out on sync_out . sync_out can also be routed to other ad7768 devices requiring simultaneous sampling and/or daisy - chaining, ensuring sync hronization of devices related to the mclk clock domain. it must then be wired to drive the sync_in pin on the same ad7768 and on the other ad7768 devices. 39 ain7+ ai positive analog input to adc channel 7. 40 ain7? ai negative analog input to adc channel 7. 41 ain6+ ai positive analog input to adc channel 6. 42 ain6? ai negative analog input to adc c hannel 6. 43 ref2+ ai reference input , positive. ref2+ is the positive reference terminal for channel 4 to channel 7. the ref2+ voltage range is from (avss + 1 v) to avdd1. apply an external differential reference voltage between ref2+ and ref2? in the ra nge from 1 v to |avdd1 ? avss |. decouple this pin to avss with a high quality capacitor, and maintain a low impedance between this capacitor and pin 46 .
data sheet ad7768 /ad7768 - 4 rev. a | page 25 of 99 pin no. mnemonic type 1 description 44 ref2? ai reference input , negative. ref2? is the negative reference terminal for channel 4 to chann el 7. the ref2? voltage range is from avss to (avdd1 ? 1 v). decouple this pin to avss with a high quality capacitor, and maintain a low impedance between this capacitor and pin 46. 45 avdd1b p analog supply voltage. this pin is 5 v 10% with respect to avss. 46 avss1b p negative analog supply. this pin is nominally 0 v. 47 ain5+ ai positive analog input to adc channel 5. 48 ain5? ai negative analog input to adc channel 5. 49 ain4+ ai positive analog input to adc channel 4. 50 ain4? ai negative analo g input to adc channel 4. 51 avss2b p negative analog supply. this pin is nominally 0 v. 52 regcapb ao analog ldo regulator output. decouple this pin to avss with a 1 f capacitor. 53 avdd2b p analog supply voltage. this pin is 2 v to 5.5 v with respect to avss. 54 avss p negative analog supply. this pin is nominally 0 v. 55, 56 format1, format0 di forma t selection pins . hardwire the formatx pins to the required values in pin control and spi control mode . these pins set the number of doutx pins used to output adc conversion data. the formatx pins are checked by the ad7768 on power - up ; the ad7768 then remains in this dat a output configuration (s ee table 31) . 57 pin /spi di pin control/spi control. this pin sets the control method. logic 0 = p in control mode for the ad7768 . pin control mode allows a pin strapped configuration of the ad7768 by tying logic input pins to required logic levels. tie the logic pins ( mode0 to mode4, dec0 and dec1, and filter ) as required for the configuration. see the pin control secti on for more details. logic 1 = spi control mode for the ad7768 . use the spi control interface signals ( cs , sclk, sdi, and sdo ) for reading and writing to the ad7768 memory map. 58 clk_sel di clock select. logic 0 = p ull this pin low for the cmos clock option. the clock is applied to pin 32 ( connect pin 31 to dgnd ). logic 1 = p ull this pin hig h for the crystal or lvds clock option. the crystal or lvds clock is applied to pin 31 and pin 32. the lvds option is available only in spi control mode. a write is required to enable the lvds clock option. 59 vcm ao common - mode voltage output. this pin o utputs (avdd1 ? avss)/2 v , which is 2.5 v by default in pin control mode. configure this pin to (avdd1 ? avss)/2 v , 2.5 v, 2.14 v, or 1.65 v in spi control mode . when driving capacitive loads larger than 0.1 f, it is recommended to place a 50 series res istor between the pin and the capacitive load for stability. the vcm voltage output is associated with the channel 0 circuitry. if channel 0 is put into standby mode, the vcm voltage output is also disabled for maximum power savings. channel 0 must be enab led while vcm is being used externally to the ad7768 . 60 avdd2a p analog supply voltage. this pin is 2 v to 5.5 v with respect to avss. 61 regcapa ao analog ldo regulator output. decoup le this pin to avss with a 1 f capacitor. 62 avss2a p negative analog supply. this pin is nominally 0 v. 63 ain0? ai negative analog input to adc channel 0. 64 ain0+ ai positive analog input to adc channel 0. 1 ai is analog input, p is power, di/o is digital input/output, di is digital input, do is digital output, and ao is analog out put.
ad7768/ad7768 - 4 data sheet rev. a | page 26 of 99 analog inputs and outputs decoupling capacitor pins supply and ground pins digital pins 6 4 a i n 0 + 6 3 a i n 0 ? 6 2 avss2a 6 1 r e g c apa 6 0 av dd 2a 5 9 v c m 5 8 c l k _sel 5 7 p i n / spi 5 6 f o r ma t 0 5 5 dgnd 5 4 a vss 5 3 a v dd 2 b 5 2 r e g c apb 5 1 a vss 2 b 5 0 a i n 2? 4 9 a i n 2+ 4 7 a i n 3+ 4 6 a vss 1 b 4 5 a v dd 1 b 4 2 a vss 4 3 r e f 2 + 4 4 r e f 2 ? 4 8 a i n 3? 4 1 a vss 4 0 a vss 3 9 a vss 3 7 st ar t 3 6 sy nc _ i n 3 5 io v d d 3 4 dr e g c ap 3 3 d g n d 3 8 sy nc _ o u t 2 a i n 1 + 3 avss1a 4 av dd 1a 7 avss 6 r e f 1 + 5 r e f 1 ? 1 a i n 1 ? 8 avss 9 avss 1 0 avss 1 2 m o d e 0 /gpio0 1 3 m o d e 1 /gpio1 1 4 m o d e 2 /gpio2 1 5 m o d e 3 /gpio3 1 6 s t 0 / c s 1 1 f il t e r /gpio4 1 7 s c l k 1 8 d e c 1 / s d i 1 9 d e c 0 / s d o 2 0 dnc/dgnd 2 1 d in 2 2 dnc 2 3 dnc 2 4 d o u t 3 2 5 d o u t 2 2 6 d o u t 1 2 7 d o u t 0 2 8 dc l k 2 9 dr dy 3 0 r eset 3 1 xt a l 1 3 2 xt a l 2 / m c l k ad 776 8-4 top view (not to scale) 14001-0 1 1 notes 1. dnc = do not connect. do not connect to this pin. figure 11 . ad7768 - 4 pin configuration table 10. ad7768 -4 pin function descriptions pin no. mnemoni c type 1 description 1 ain1? ai negative analog input to adc channel 1. 2 ain1+ ai positive analog input to adc channel 1. 3 avss1a p negative analog supply. this pin is nominally 0 v. 4 avdd1a p analog supply voltage , 5 v 10% with respect to avss. 5 ref1? ai reference inp ut negative. ref1 ? is the negative reference terminal for channel 0 and channel 1. the ref1 ? voltage range is from avss to (avdd1 ? 1 v). decouple this pin to avss with a high quality capacitor, and maintain a low impedance between this capacitor and pin 3 . 6 ref1+ ai reference input positive. ref1+ is the positive reference terminal for channel 0 and channel 1. the ref1+ voltage range is from (avss + 1 v) to avdd1. apply an external differential reference voltage between ref1+ and ref1 ? in the range from 1 v to |avdd1 ? avss |. decouple this pin to avss with a high quality capacitor, and maintain a low impedance between this capacitor and pin 3. 7 to 10, 39 to 42 , 54 avss ai negative analog supply. this pin is nominally 0 v. 11 filter/gpio4 di/o filter s elect/general - purpose input - output. in pin control mode , this pin selects the filter type. set this pin to logic 1 for the sinc5 filter. this sinc5 filter is a low latency filter, and is best for dc applications or where a user has specialized postfil tering implemented off chip. set this pin to logic 0 for the wideband low ripple filter response. this filter has a steep transition band and 105 db stop band attenuation. full attenuation at nyquist (odr/2) means that no aliasing occurs at odr/2 out t o the first chopping zone. when in spi control mode, this pin can be used as a general - purpose input/output (gpio4). see table 75 for more details.
data sheet ad7768 /ad7768 - 4 rev. a | page 27 of 99 pin no. mnemoni c type 1 description 12, 13, 14, 15 mode0/gpio0, mode1/gpio1, mode2/gpio2, mode3/g pio3 di/di/o mode selection/general - purpose input/output pin 0 to pin 3. in pin control mode, the modex pins set the mode of operation for all adc channels, controlling power consumption, dclk frequency, and the adc conversion type, allowing one - shot conversion operation. in spi control mode, the gpiox pins, in addition to the filter/gpio4 pin, form five general - purpose input/output pins (gpio4 to gpio0). see table 75 for more details. 16 st0/ cs di standby 0/chip select input. in pin control mode, a logic 1 on this pin places channel 0 to channel 3 into standby mode. in spi control mode, this pin is the active low chip select input to the spi control interface. the vcm volta ge output is associated with the channel 0 circuitry. if channel 0 is put into standby mode, the vcm voltage output is also disabled for maximum power savings. channel0 must be enabled while vcm is being used externally to the ad7768 - 4 . the crystal excitation circuitry is associated with the channel 2 circuitry. if channel 2 is put into standby mode, the crystal circuitry is also disabled for maximum power savings. channel 2 must be enabl ed while the external crystal is used on the ad7768 -4. 17 sclk di serial clock input. in spi control mode, this pin is the serial clock input pin for the spi control interface. in pin control mode, tie this pin to a logic 0 or dgnd. 18 dec1/sdi di decimation rate control input 1/serial data input. in pin control mode, the dec0 and dec1 pins configure the decimation rate for all adc channels. see table 17 in the setting the decimation rate section. in spi control mode, this pin is the serial data input pin used to write data to the ad7768 -4 register bank. 19 dec0/sdo di/o decimation rate control input 0/serial data output. in pin control mode, the dec0 and dec1 pins configure the decimation rate for all adc channels. see t able 17 in the setting the decimation rate section. in spi control mode, this pin is the serial data output pin, allowing readback from the ad7768 -4 registers. 20 dnc/dgnd do/di do not connect/digital ground. this is an unused p in. leave this pin floating if format0 is tied to logic low . if format0 is tied to logic high , connect this pin to dgnd through a pull - down resistor. 21 din di data in put daisy chain. this pin acts as a digital input from a separate ad7768 -4 device if configured in a synchronized multidevice daisy - chain. to use this pin in a daisy - chain, hardwire t he format0 pin to logic high. if format0 is tied to logic low, or the daisy chaining input pin is not used , then tie this pin to dgnd through a pull - down resistor . 22, 23 dnc do do not connect. do not connect to this pin. 24 dout3 do conversion data outp ut 3. this pin is synchronous to dclk and framed by drdy . 25 dout2 do conversion data output 2. this pin is synchronous to dclk and framed by drdy . 26 dout1 do conversion data output 1. this pin is synchronous to dclk and framed by drdy . 27 dout0 do conversion data output 0. this pin is synchronous to dclk and framed by drdy 28 dclk do adc conversion data clock. this pin clocks conversion data out to the digital host (dsp /fpga). thi s pin is synchronous with drdy and any conversion data output on dout0 to dout 3 and is derived from the mclk signal. this pin is unrelated to the control spi interface. 29 drdy do data ready. drdy is a p eriodic signal output framing the conversion results from the four adcs. this pin is synchronous to dclk and dout0 to dout 3. 30 reset di hardware asynchronous reset input. after the device is fully powered up, it is recommended to per form a hard reset using this pin or, alternatively, to perform a soft reset by issuing a reset over the spi control interface 31 xtal1 di input 1 for crystal or connection to an lvds clock. when clk_sel is 0, connect xtal1 to dgnd. when used with an lvds clock, it is recommended that this pin be connected to one trace of the lvds signal pair. when used as an lvds input, a rising edge on this pin is detected as a rising mclk edge by the ad7768 - 4.
ad7768/ad7768 - 4 data sheet rev. a | page 28 of 99 pin no. mnemoni c type 1 description 32 xtal2/mclk di input 2 for cmos/crystal/lvds sampling clock. see the clk_sel pin for the details of this configuration. external crystal: xtal2 is connected to the external crystal. lvds: w hen used with an lvds clock, connect this pin to the second trace of the lvds signal pair. cmos clock: this pin operates as an mclk input. this pin is a cmos input with logic level of iovdd/dgnd. when used as a cmos clock input, a rising edge on this pin is detected as a rising mclk edge by the ad7768 -4. 33 dgnd p digital ground. nominally gnd (0 v). 34 dregcap ao digital ldo regulator output. decouple this pin to dgnd with a high quality, low esr, 10 f capacitor. for optimum performance, use a decoupling capacitor with an esr specification of less than 400 m . this pin is not for use in circuits external to the ad7768 -4. for 1.8 v iovdd ope ration, connect this pin to iovdd via an external trace to provide power to the digital processing core. 35 iovdd p digital supply. this pin sets the logic levels for all interface pins. iovdd also powers the digital processing core, via the digital ldo, when iovdd is at least 2.25 v. for 1.8 v iovdd operation, connect this pin to dregcap via an external trace to provide power to the digital processing core. 36 sync_in di synchronization input. sync_in receives the sync hronous signal from sync_out . it is used in the synchronization of any ad7768 -4 that requires simultaneous sampling or is in a daisy chain. the user can ignore the start and sync_out function if the ad7768 -4 sync_in pin is connected to the system synchronization pulse. this signal pulse must be sync hronous to the mclk clock domain. 37 start di start signal. the start pulse acts to synchronize the ad7768 -4 to other devices. the signal can be asyn chronous. the ad7768 -4 samples the input and then outputs a sync_out pulse. this sync_out pulse must be routed to the sync_in pin of this device, and any other ad7768 -4 devices that must be synchronized together. this means that the user does not need to run the adcs and their digital host from the same clock domain , which is u seful when there are long traces or back planes between the adc and the controller. if this pin is not used , it must be tied to a logic 1 through a pull - up resistor. in a daisy - chained system of ad7768 -4 devices, two successive synchronization pulses must be applied to guarantee that all adcs are synchronized. two synchronization pulses are also required in a system of more than one ad7768 -4 device sharing a single mclk signal, where the drdy pin of only one device is used to detect new data. 38 sync_out do synchronization output. this pin operates only when the start input is used. when using the start input feature, the sync_out must be connected to sync_in via an external trace. sync_out is a digital output that is synchronous to th e mclk signal; the synchroniza - tion signal driven in on start is internally synchronized to the mclk signal and is driven out on sync_out . sync_out can also be routed to other ad7768 -4 devices requiring simultane ous sampling and/or daisy - chaining, ensuring synchronization of devices related to the mclk clock domain. it must then be wired to drive the sync_in pin on t he same ad7768 -4 and on the other ad7768 -4 devices. 43 ref2+ ai reference input positive. ref2+ is the positive ref erence terminal for channel 2 and channel 3. the ref2+ voltage range is from (avss + 1 v) to avdd1. apply an external differential reference voltage between ref2+ and ref2 ? in the range from 1 v to |avdd1 ? avss |. decouple this pin to avss with a high qual ity capacitor, and maintain a low impedance between this capacitor and pin 3. 44 ref2? ai reference input negative. ref2 ? is the negative reference terminal for channel 2 and channel 3. the ref2? voltage range is from avss to (avdd1 ? 1 v). decouple this pin to avss with a high quality capacitor, and maintain a low impedance between this capacitor and pin 3. 45 avdd1b p analog supply voltage. this pin is 5 v 10% with respect to avss. 46 avss1b p negative analog supply. this pin is nominally 0 v. 47 ai n3+ ai positive analog input to adc channel 3. 48 ain3? ai negative analog input to adc channel 3. 49 ain2+ ai positive analog input to adc channel 2. 50 ain2? ai negative analog input to adc channel 2. 51 avss2b p negative analog supply. this pin is nominally 0 v. 52 regcapb ao analog ldo regulator o utput. decouple this pin to avss with a 1 f capacitor.
data sheet ad7768 /ad7768 - 4 rev. a | page 29 of 99 pin no. mnemoni c type 1 description 53 avdd2b p analog supply voltage. 2 v to 5.5 v with respect to avss. 55 dgnd p digital ground. this pin is nominally 0 v. 56 format0 di format selection. hardwire the format0 pin to the required v alue in pin and spi control mode . t his pin sets the number of dout x pins used to output adc conversion data. the format0 pin is checked by the ad7768 -4 on power - up, the ad7768 -4 then remains in this data output configuration. see table 32. 57 pin /spi di pin control/spi control. this pin sets the ad7768 -4 control method. logic 0 = p in control mode for the ad7768 -4. pin control mode a llows pin strapped configuration of t he ad7768 -4 by tying logic input pins to required logic levels. tie logic pins mode0 to mode4, dec0 and dec1, and filter as required for the configuration. see the pin control section for more details. logic 1 = spi control mode for the ad7768 -4 . use the spi control interface signals ( cs , sclk, sdi, and sdo ) for reading and writing to the ad7768 -4 memor y map. 58 clk_sel di clock select. logic 0 = pull this pin low for the cmos clock option. the clock is applied to pin 32 ( connect pin 31 to dgnd). logic 1 = pull this pin high for the crystal or lvds clock option. the crystal or lvds clock is applied to pin 31 and pin 32. the lvds option is available only in spi control mode. a write is required to enable the lvds clock option. 59 vcm ao common - mode voltage output. this pin output s (avdd1 ? avss)/2 v , which is 2 .5 v by default in pin control mode. con f igur e this pin to (avdd1 ? avss)/2 v , 2.5 v, 2.14 v, or 1.65 v in sp control mode . when driving capacitive loads larger than 0.1 f, it is recommended to place a 50 series resistor between the pin and the capacitive load for stability. the vcm voltage output is associated with the channel 0 circuitry. if channel 0 is put into standby mode, the vcm voltage output is also disabled for m aximum power savings. channel 0 must be enabled while vcm is being used externally to the ad7768 -4. 60 avdd2a p analog supply voltage. this pin is 2 v to 5.5 v with respect to avss. 61 regcapa ao analog ldo regulator output. decouple this pin to avss with a 1 f capacitor. 62 avss2a p negative analog supply. this pin is nominally 0 v. 63 ain0? ai negative analog input to adc channel 0. 64 ain0+ ai positive analog input to adc channel 0. 1 ai is analog input, p is power, di/o is digital input/output, di is digital input, do is digital output, and ao is analog output.
ad7768/ad7768 - 4 data sheet rev. a | page 30 of 99 typical performance characteristics avdd1 = 5 v, avdd2 = 2.5 v , avss = 0 v , iovdd = 2.5 v, v ref = 4.096 v, t a = 25c, fast power mode, w ideband f ilte r, decimat ion = 32, mclk = 32.768 mhz, a nalog i nput p recharge b uffers on , reference precharge b uffers off , unless otherwise noted. ?200 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 10 100k 10k 1k 100 amplitude (db) frequency (hz) 14001-012 snr = 107.8db thd = ?126.4db figure 12 . fft, fast mode, wideband filter, ?0.5 dbfs ?200 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 10 100k 10k 1k 100 amplitude (db) frequency (hz) 14001-014 snr = 107.9db thd = ?129.3db figure 13 . fft, median mode, wideband filter, ?0.5 dbfs ?200 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 10 10k 1k 100 amplitude (db) frequency (hz) 14001-016 snr = 108.0db thd = ?129.7db figure 14 . fft, eco mode, wideband filter, ?0.5 dbfs ?200 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 10 100k 10k 1k 100 amplitude (db) frequency (hz) 14001-018 snr = 107.9db thd = ?129.8db figure 15 . fft, fast mode, wideband filter, ?6 dbfs ?200 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 10 100k 10k 1k 100 amplitude (db) frequency (hz) 14001-020 snr = 108.1db thd = ?128.8db figure 16 . fft, median mode, wideband filter, ?6 dbfs ?200 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 10 10k 1k 100 amplitude (db) frequency (hz) 14001-022 snr = 108.1db thd = ?129.7db figure 17 . fft, eco mode, wideband filter, ?6 dbfs
data sheet ad7768 /ad7768 - 4 rev. a | page 31 of 99 ?200 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 10 100k 10k 1k 100 amplitude (db) frequency (hz) 14001-013 snr = 111.1db thd = ?126.5db figure 18 . fft, fast mode, sinc5 filter, ?0.5 dbfs ?200 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 10 100k 10k 1k 100 amplitude (db) frequency (hz) 14001-015 snr = 111.1db thd = ?128.8db figure 19 . fft, median mod e, sinc5 filter, ?0.5 dbfs ?200 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 10 10k 1k 100 amplitude (db) frequency (hz) 14001-017 snr = 111.1db thd = ?130.1db figure 20 . fft, eco mode, sinc5 filter, ?0.5 dbfs ?200 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 10 100k 10k 1k 100 amplitude (db) frequency (hz) 14001-019 snr = 111.1db thd = ?129.3db figure 21 . fft, fast mode, sinc5 filter, 6 dbfs ?200 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 10 100k 10k 1k 100 amplitude (db) frequency (hz) 14001-021 snr = 111.1db thd = ?130.2db figure 22 . fft, median mode, sinc5 filter , 6 dbfs ?200 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 10 10k 1k 100 amplitude (db) frequency (hz) 14001-023 snr = 111.5db thd = ?131.7db figure 23 . fft, eco mode, sinc5 filter, ?6 dbfs
ad7768/ad7768 - 4 data sheet rev. a | page 32 of 99 ?200 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 5 5000 500 50 amplitude (db) frequency (hz) 14001-026 snr = 113.3db thd = ?130.8db f s = 8.192khz f in = 1khz figure 24 . fft one - shot - mode, sinc5 filter, median mode, decimation = 64, ?0.5 dbfs, sync_in frequency = mclk/4000 ?200 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 100 100k 10k 1k amplitude (db) frequency (hz) 14001-276 second-order imd = ?135.2db third-order imd = ?129.3db figure 25 . imd with input signals at 9.7 khz and 10.3 khz 0 50 100 150 200 shorted noise (v) number of occurrences 14001-028 ?45 ?41 ?37 ?34 ?30 ?26 ?22 ?18 ?15 ?11 ?7 ?3 1 4 8 12 16 20 23 27 31 35 39 42 fast median eco figure 26 . shorted noise, wideband filter 0 50 100 150 250 200 shorted noise (v) number of occurrences 14001-029 fast median eco ?45 ?41 ?38 ?34 ?31 ?27 ?23 ?20 ?16 ?13 ?9 ?5 ?2 2 5 9 13 16 20 23 27 31 34 38 41 45 figure 27 . shorted noise , sinc5 filter 0 50 200 150 100 number of occurrences shorted noise (v) 14001-057 ?40c +25c +105c ?50 ?46 ?42 ?38 ?34 ?30 ?26 ?22 ?18 ?14 ?10 ?6 ?2 2 6 10 14 18 22 26 30 34 38 42 46 50 figure 28 . shorted noise vs. temperature , wideband filter 5 6 7 8 9 10 1 1 13 14 15 ?40 ?30 ?35 ?25 ?15 ?20 ?10 ?5 5 15 0 10 20 25 35 35 45 40 55 50 65 60 75 70 85 80 95 90 100 105 rms noise (v) 12 wideband sinc5 temperature (c) 14001-058 figure 29 . rms noise vs. temperature, fast mode
data sheet ad7768 /ad7768 - 4 rev. a | page 33 of 99 5 6 7 8 9 10 1 1 13 14 15 ?40 ?30 ?35 ?25 ?15 ?20 ?10 ?5 5 15 0 10 20 25 35 35 45 40 55 50 65 60 75 70 85 80 95 90 100 105 rms noise (v) 12 wideband sinc5 temperature (c) 14001-059 figure 30 . rms noise vs. temperature, median mode 5 6 7 8 9 10 1 1 13 14 15 ?40 ?30 ?35 ?25 ?15 ?20 ?10 ?5 5 15 0 10 20 25 35 35 45 40 55 50 65 60 75 70 85 80 95 90 100 105 rms noise (v) 12 wideband sinc5 temperature (c) 14001-060 figure 31 . rms noise vs. temperature, eco mode 10.0 10.2 10.4 10.6 10.8 1 1.0 1 1.2 1 1.4 1 1.6 1 1.8 12.0 0 1 2 3 4 5 6 7 rms noise (v) channe l v ref = 5.00v v ref = 4.096v v ref = 2.500v 14001-061 figure 32 . rms noise per channel for various v ref values ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 1 2 3 4 5 6 7 amplitude (db) channe l 14001-175 f in = 3.15khz interferer (1khz) on all other channels figure 33 . crosstalk ?180 ?170 ?160 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 80 90 100 110 0 5 10 15 20 25 30 35 40 thd and thd + n (db) snr and dynamic range (db) mclk frequency (mhz) snr, fast dynamic range, fast thd, fast thd + n, fast 14001-062 f in = 1khz figure 34 . snr, dynamic range, thd, and thd +n vs. mclk frequency ?180 ?160 ?140 ?120 ?100 thd (db) ?80 ?60 ?40 ?20 0 10 100 1k input frequenc y (hz) 10k 100k f a s t m e d ian e co 14001-034 figure 35 . thd vs. input frequency, three power modes, wideband filter
ad7768/ad7768 - 4 data sheet rev. a | page 34 of 99 ?180 ?160 ?140 ?120 ?100 thd (db) ?80 ?60 ?40 ?20 0 10 100 1k input frequenc y (hz) 10k 100k f a s t m e d ian e c o 14001-035 figure 36 . thd vs. input frequency, three power modes, sinc5 filter 0 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 thd and thd + n (db) input amplitude (dbfs) 14001-307 f in = 1khz fast thd fast thd + n median thd median thd + n eco thd eco thd + n figure 37. thd and thd + n vs. input amplit ude , wideband filter 0 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 thd and thd + n (db) input amplitude (dbfs) f in = 1khz 14001-308 f in = 1khz fast thd fast thd + n median thd median thd + n eco thd eco thd + n figure 38 . thd and thd + n vs. input amplitude , sinc5 filter 14001-309 120 100 102 104 106 108 110 112 114 116 118 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 snr (db) input amplitude (dbfs) fast mode, sinc5 filter median mode, sinc5 filter eco mode, sinc5 filter fast mode, wideband filter median mode, wideband filter eco mode, wideband filter figure 39 . snr vs. input amplitude ?4 ?3 ?2 ?1 0 1 2 3 4 in l error (ppm) input vo lt age (v) ?v ref 0v +v ref v ref = 2.500v v ref = 4.096v v ref = 5.000v 14001-052 figure 40 . inl e rror vs. input voltage for various voltage reference (v ref ) levels, fast mode ?4 ?3 ?2 ?1 0 1 2 3 4 in l error (ppm) input vo lt age (v) ? v ref 0 v + v ref v ref = 2.500v v ref = 4.096v v ref = 5.000v 14001-053 figure 41 . inl error vs. input voltage for various voltage reference (v ref ) levels, median mode
data sheet ad7768 /ad7768 - 4 rev. a | page 35 of 99 ?4 ?3 ?2 ?1 0 1 2 3 4 in l error (ppm) input vo lt age (v) ? v ref 0 v + v ref v ref = 2.500v v ref = 4.096v v ref = 5.000v 14001-054 figure 42 . inl error vs . input voltage for various voltage reference (v ref ) levels, eco mode ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 in l error (ppm) input vo lt age (v) ? v ref 0 v + v ref f u l l s c al e ( ? 4 . 01 5 v t o + 4 . 01 5 v ) h al f s c a l e ( ? 2 . 0 08 v t o + 2 . 0 08 v ) quarter scale ( ? 1 . 0 04 v t o + 1 . 0 04 v ) 14001-055 figure 43 . inl error vs. input voltage, full - scale, half - scale, and quarter - scale inputs ?3 ?2 ?1 0 1 2 3 ?4.0 ?3.7 ?3.4 ?3.1 ?2.7 ?2.4 ?2.1 ?1.8 ?1.4 ?1.1 ?0.8 ?0.5 ?0.2 0.2 0.5 0.8 1.1 1.4 1.8 2.1 2.4 2.7 3.1 3.4 3.7 4.0 in l error (ppm) input vo lt age (v) +25 c 0 c +85 c +105 c ?40 c 14001-056 figure 44 . inl error vs. input voltag e for various temperatures, fast mode 0 10 20 30 40 50 ?60 ?50 ?40 ?30 ?20 ?10 0 10 20 offset error (v) number of occurrences 14001-403 +105c +25c ?40c figure 45 . offset error distribution , dclk = 24 mhz 0 10 20 30 40 50 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 20 40 offset error (v) number of occurrences 14001-404 +105c +25c ?40c figure 46 . offset error distribution, dclk = 32 mhz 120 100 80 60 40 20 0 ?150 ?100 ?50 0 50 100 150 200 250 300 350 number of occurrences offset error drift (nv/c) 14001-401 figure 47 . offset error drift, dclk = 24 mhz
ad7768/ad7768 - 4 data sheet rev. a | page 36 of 99 45 40 35 30 25 20 15 10 5 0 ?350 ?300 ?250 ?200 ?150 ?100 ?50 0 50 100 150 200 250 300 350 number of occurrences offset error drift (nv/c) 14001-402 figure 48 . offset error drift, dclk = 32 mhz 0 100 200 300 400 500 600 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 offset drift (nv/c) dclk frequenc y (mhz) 1.8 v i o v d d 2.5 v i o v d d 14001-040 figure 49 . offset drift vs. dclk frequency ? 40 25 105 temper a ture (c) 0 20 40 60 80 100 120 offset error m a tching (v) f ast m o d e median m o d e e c o m o d e 14001-047 figure 5 0 . channel offset error matching 0 100 200 300 400 500 600 gain error (ppm) number of occurrences 14001-405 +105c +25c ?40c ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 10 15 20 25 30 35 figure 51 . gain error distribution 0 10 20 30 40 50 60 2 3 4 5 6 7 8 9 10 1 1 12 numeber of occurrences gain error (ppm) 14001-046 figure 52 . channel to channel gain error matching ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 10 100 1k 10k 100k 1m 10m ac cmrr (db) input frequency (hz) 14001-063 figure 53 . ac cmrr vs. input frequency
data sheet ad7768 /ad7768 - 4 rev. a | page 37 of 99 0 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 100 1k 10k 100k 1m 10m ac psrr (db) frequency (hz) 14001-310 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 dclk = 32.768mhz avdd1 = 5v + 100mv p-p figure 54 . ac psrr vs. freq uency, avdd1 0 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 100 1k 10k 100k 1m 10m ac psrr (db) frequency (hz) 14001-311 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 dclk = 32.768mhz avdd2 = 5v + 100mv p-p figure 55 . ac psrr vs. frequency, avdd2 ? 1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 100 1k 10k 100k 1m 10m ac psrr (db) frequenc y (hz) iovdd = 1.8v, dclk = 32.768mhz, ch 7 iovdd = 2.5v, dclk = 32.768mhz, ch 7 iovdd = 1.8v, dclk = 8.192mhz, ch 7 iovdd = 2.5v, dclk = 8.192mhz, ch 7 14001-065 figure 56 . ac psrr vs. frequency , iovdd ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 20 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 normalized input frequency ( f in / f odr ) amplitude (db) eco median f ast 14001-074 figure 57 . wideband filter profile, amplitude vs. f in /f odr 0 2000000 4000000 6000000 8000000 10000000 12000000 14000000 16000000 18000000 d out (code) a in (v) samples 14001-071 ?4 ?3 ?2 ?1 0 1 2 3 4 5 0 10 20 30 40 50 60 70 80 a in d out figure 58 . step response, wideband filter ?0.005 ?0.004 ?0.003 ?0.002 ?0.001 0 0.001 0.002 0.003 0.004 0.005 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 amplitude (db) normalized input frequency ( f in / f odr ) eco median f ast 14001-072 figure 59 . wideband filter ripple
ad7768/ad7768-4 data sheet rev. a | page 38 of 99 ?200 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0123456 amplitude (db) normalized input frequency ( f in / f odr ) measurement limit = 130db 14001-073 figure 60. sinc5 filter profile, amplitude vs. f in /f odr 0 2000000 4000000 6000000 8000000 10000000 12000000 14000000 16000000 18000000 0 5 10 15 20 25 30 d out (code) a in (v) samples 14001-070 ?4 ?3 ?2 ?1 0 1 2 3 4 5 a in d out figure 61. step response, sinc5 filter ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 ? 40 25 105 temperature (c) analog input current (a) common-mode component, no precharge (a/v) differential component, no precharge (a/v) total current, precharge on (a) 14001-051 figure 62. analog input current vs. temperature, analog input precharge buffers on/off ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 ?4025105 reference input current (a/v/channel) temperature (c) fast, no precharge median, no precharge eco, no precharge fast with precharge median with precharge eco with precharge 14001-050 figure 63. reference input current vs. temperature, reference precharge buffers on/off 120 100 80 60 40 20 0 2.47 2.46 2.45 2.44 2.43 2.42 number of occurrences v cm (v) 14001-312 avdd1 = 5v, avss = 0v vcm_vsel = 10 part to part distribution figure 64. vcm output voltage distribution 0 5 10 15 20 25 30 35 40 ?40 ?25 ?10 5 20 35 50 65 80 95 110 supply current (ma) temperature (c) eco fast median 14001-066 figure 65. supply current vs. temperature, avdd1
data sheet ad7768 /ad7768 - 4 rev. a | page 39 of 99 0 5 10 15 20 25 30 35 40 ?40 ?25 ?10 5 20 35 50 65 80 95 1 10 supp l y current (ma) temper a ture (c) eco fast median 14001-067 figure 66 . supply current vs. temperature, avdd2 ?40 ?25 ?10 5 20 35 50 65 80 95 1 10 supp l y current (ma) temper a ture (c) 0 10 20 30 40 50 60 70 e c o , sinc5 e c o , wi d e b a n d f a st , sinc5 f a st , wid e b a n d me d i a n , sinc5 me d i a n , wideband 14001-068 figure 67 . supply current vs. temperature, iovdd 0 50 100 150 200 250 300 350 400 450 500 ?40 25 105 t o t a l power (mw) f as t , sinc5 fi l ter median, sinc5 fi l ter e co, sinc5 fi l ter f as t , wideband fi l ter median, wideband fi l ter eco, wideband fi l ter temper a ture (c) 14001-069 figure 68 . total power vs. temperature
ad7768/ad7768 - 4 data sheet rev. a | page 40 of 99 terminology ac common - mode rejection ratio ( ac cmrr) ac cmrr is defined as the ratio of the power in the adc output at frequency , f, to the power of a sine wave applied to the common - mode voltage of a in x + and a in x ? at frequency, f s . ac cmrr (db) = 10 log( pf / pf s ) where : pf is the power at frequency, f , in the adc outpu t. pf s is the power at frequency, f s , in the adc output. gain error the first transition (from 100 000 to 100 001) occurs at a level ? lsb above n ominal negative full scale (?4.0959375 v for the 4.096 v range). the last transition (from 011 110 to 011 111) occurs for an analog voltage 1? lsb below the nominal full scale (+4.0959375 v for the 4.096 v range). the gain error is the deviation of t he difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. gain error drift gain error drift is t he gain error change due to a temperature change of 1c. it is ex pressed in parts per million per degree celsius. integral nonlinearity (inl) error inl error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occur s ? lsb before the first code transition. positive full scale is defined as a level 1? lsb beyond the last code transition. the deviation is measured from the middle of each code to the true straight line. intermodulation distortion (imd) with inputs consi sting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at the sum and difference frequencies of mfa and nfb, where m, n = 0, 1, 2, 3, and so on. intermodulation distortion terms are those for wh ich neither m or n are equal to 0. for example, the second - order terms include (fa + fb) and (fa ? fb), and the third - order terms include (2fa + fb), (2fa ? fb), (fa + 2fb), and (fa ? 2fb). the ad7768 / ad7768 - 4 are tested using the ccif standard, where two input frequencies near to each other are used. in this case, the second - order terms are usually distanced in frequency from the original sine waves, and the third - order terms are usually at a frequency close to the input frequencies. as a result, the second - order and third - order terms are specified separately. the calculation of the intermodulation distortion is as per the thd specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals , expressed in decibels. least significant bit (lsb) the least significant bit, or lsb, is the smallest increment that can be represented by a converter. for a fully differential input adc with n bits of resolution, the lsb expressed in volts is as follows : lsb (v) = (2 v ref )/2 n for the ad7768 / ad7768 - 4 , v ref is the difference voltage between the ref x + and r efx? pins, and n = 24. offset error offset error is the difference between the ideal midscale input voltage (0 v) and the actual voltage producing the midscale output code. power supply rejection ratio (psrr) variations in power supply affect the full - scal e transition but not the linearity of the converter. psrr is the maximum change in the full - scale transition point due to a change in the power supply voltage from the nominal value. signal -to - noise ratio (snr) snr is the ratio of the rms value of the actu al input signal to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in decibels. signal -to - noise - and - distortion ratio (sinad) sinad is the ratio of the rms value of the ac tual input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for sinad is expressed in decibels. spurious - free dynamic range (sfdr) sfdr is the difference, in decibels, betwe en the rms amplitude of the input signal and the peak spurious signal ( excluding the first five harmonics). total harmonic distortion (thd) thd is the ratio of the rms sum of the first five harmonic components to the rms value of a full - scale input signal and is expressed in decibels.
data sheet ad7768/ad7768-4 rev. a | page 41 of 99 theory of operation the ad7768 and ad7768-4 are 8-channel and 4-channel, simultaneously sampled, low noise, 24-bit - adcs, respectively. each adc within the ad7768/ ad7768-4 employs a - modula- tor whose clock runs at a frequency of f mod . the modulator samples the inputs at a rate of 2 f mod to convert the analog input into an equivalent digital representation. these samples therefore represent a quantized version of the analog input signal. the - conversion technique is an oversampled architecture. this oversampled approach spreads the quantization noise over a wide frequency band (see figure 69). to reduce the quantization noise in the signal band, the high order modulator shapes the noise spectrum so that most of the noise energy is shifted out of the band of interest (see figure 70). the digital filter that follows the modulator removes the large out of band quantization noise (see figure 71). for further information on the basics as well as more advanced concepts of - adcs, see the mt-022 tutorial and the mt-023 tutorial . digital filtering has certain advantages over analog filtering. first, it is insensitive to component tolerances and the variation of component parameters over time and temperature. because digital filtering on the ad7768/ ad7768-4 occurs after the analog to digital conversion, it can remove some of the noise injected during the conversion process; analog filtering cannot remove noise injected during conversion. second, the digital filter com- bines low pass-band ripple with a steep roll-off, and high stop band attenuation, while also maintaining a linear phase response, which is difficult to achieve in an analog filter implementation. quantization noise f mod /2 band of interest 14001-075 figure 69. - adc quantization noise (linear scale x-axis) noise shaping band of interest 14001-176 f mod /2 figure 70. - adc noise shaping (linear scale x-axis) digital filter cutoff frequency band of interest 14001-177 f mod /2 figure 71. - adc digital filter cutoff frequency (linear scale x-axis) clocking, sampling tr ee, and power scaling the ad7768 / ad7768-4 include multiple adc cores. each of these adcs receives the same master clock signal, mclk. the mclk signal can be sourced from one of three options: a cmos clock, a crystal connected between the xtal1 and xtal2 pins, or in the form of an lvds signal. the mclk signal received by the ad7768/ ad7768-4 defines the modulator clock rate, f mod , and, in turn, the sampling frequency of the modulator of 2 f mod . the same mclk signal is also used to define the digital output clock, dclk. the f mod and dclk internal signals are synchronous with mclk. figure 72 illustrates the clock tree from the mclk input to the modulator, the digital filter, and the dclk output. there are divider settings for mclk and dclk. these dividers in conjunction with the power mode and digital filter decimation settings are key to ad7768/ ad7768-4 operation. the ad7768/ ad7768-4 have the ability to scale power consump- tion vs. the input bandwidth or noise desired. the user controls two parameters to achieve this: mclk division and power mode. combined, these two settings determine the clock frequency of the modulator (f mod ) and the bias current supplied to each modulator. the power mode (fast, median, or eco) sets the noise, speed capability, and current consumption of the modulator. it is the dominant control for scaling the power consumption of the adc. all settings of mclk division and power mode apply to all adc channels. dclk_div 00: dclk = mclk/8 01: dclk = mclk/4 10: dclk = mclk/2 11: dclk = mclk/1 mclk_div mclk/4 mclk/8 mclk/32 power modes: fast median eco decimation rates = x32, x64, x128, x256, x512, x1024 digital filter dclk drdy doutx data interface control adc modulator 14001-076 figure 72. sampling structure, defi ned by mclk, dclk_div, and mclk_div settings the modulator clock frequency (f mod ) is determined by selecting one of three clock divider settings: mclk/4, mclk/8, or mclk/32. although the mclk division and power modes are independent settings, there are restrictions that must be adhered to. a valid range of modulator frequencies exists for each power mode. table 11 describes this recommended range, which allows the device to achieve the best performance while minimizing power consumption. the ad7768/ ad7768-4 specifications do not cover the performance and function beyond the maximum f mod for a given power mode.
ad7768/ad7768 - 4 data sheet rev. a | page 42 of 99 for example, in fast mode , to maximize the speed of co nversion or input bandwidth , an mclk of 32.768 mhz is required and mclk_div = 4 must be selected for a modulator frequency of 8.192 mhz. table 11 . recommended f mod range for each power mode power mode recommended f mod (mhz) range , mclk = 32.768 mhz eco 0.036 to 1.024 median 1.024 to 4.096 fast 4.096 to 8.192 control of the settings for power mode, the modulator frequency and the data clock frequency differs in pin control mode vs . spi control mode. in spi control mode, the user can program the power mode, mclk divider (mclk_div) , and dclk frequency using register 0x04 and register 0x07 (see table 42 and table 45 for register information for the ad776 8 or table 68 and table 71 for the ad7768 - 4 ). independent selection of the power mode and mclk_div allows full freedom in the mclk speed selection to achieve a target modulator frequency. in pin control mode, the modex pins determine the power mode, modulator frequency, and dclk frequency. the modulator frequency tracks the power mode. this means that f mod is fixed at mclk/32 for eco mode, mclk/8 for median mode, and mclk/4 for fast mode (see table 20). example of power vs . noise performance optimization depending on the bandwidth of interest for the measurement , the user can choose a strategy of either lowest current consump - tion or highest resolution. this choice is due to an overlap in the coverage of each power mode . the device s offer the ability to balance the mclk division ratio with the rate of decimation (averaging) set in the digital filter. lower power can be achieved by using lower modulator clock frequencies. conversely, the highest resolution can be achieved by using higher modulator clock frequencies and maximizing the amount of oversampling. as an e xample, consider a system constraint with a maximum available mclk of 16 mhz . the system is targeting a measure - ment bandwidth of approximately 25 khz with the wideband filter , setting the output data rate of the ad7768 / ad7768 - 4 to 62.5 khz. because of the low mclk frequency available and system power budget , median power mode is used . in m edian power mode , this 25 khz input bandwidth can be achieved by setting the mclk division and decim ation ratio to balance , using two configurations. this flexibility is possible in spi control mode only. configuration a to maximize the d ynamic r ange , use the following settings: ? mclk = 16 mhz ? median power ? f mod = mclk/4 ? decimation = 64 (digital filter se tting) ? odr = 62.5 khz this configuration maximizes the available decimation rate (or oversampling ratio) for the bandwidth required and mclk rate available. the decimation averages the noise from the modulator , maximizing the dynamic range. configuration b to m inimize p ower , use the following settings: ? mclk = 16 mhz ? median power ? f mod = mclk/8 ? decimation = 32 (digital filter setting) ? odr = 62.5 khz this configuration reduces the clocking speed of the modulator and the digital filter. compared to configurat ion a , configuration b saves 48 mw of power. the trade - off in the case of configuration b is tha t the digital filter must run at a 2 lower decimation rate. this 2 reduction in decimation rate (or oversampling ratio) results in a 3 db reduction in the dyn amic range vs . configuration a . clocking out the adc conversion results (dclk) the ad7768 / ad7768 - 4 dclk is a divided version of the master clock input. as shown in figure 72, the dclk_div setting determines the speed of the dclk. dclk is a continuous clock. the user can set the dclk frequency rate to one of four divisions of mclk: mclk/1, mclk/2, mclk/4, and mclk/8. because there are eight chann els and 32 bits of data per conversion , the conversion time and the setting of dclk directly determine the number of data output lines that are required via the format 0 and format1 pin settings on the ad7768 , or the format0 pin on the ad7768 - 4 . th us , the intended minimum d ecimation and desired dclk_div setting must be understood prior to choosing the setting of the format x pins. noise performance an d resolution table 12 and table 13 show the noise performance for the wideband and sinc5 digital filters of the ad7768 / ad7768 - 4 for various output data rates and power modes. the noise values and dynamic range specified are typical for the bipolar input range with an external 4.096 v referen ce (v ref ). the rms noise is measured with shorted analog inputs, which are driven to (avdd1 ? avss)/2 using the on - board vcm buffer output. the dynamic range is calculated as the ratio of the rms shorted input noise to the rms full - scale input signal range. dynam ic range ( db ) = 20log 10 ((2 v ref /22)/( rms noise ) the lsb size with 4.096 v reference is 488 nv, and is calculated as follows: lsb (v) = (2 v ref )/2 24
ad7768/ad7768 - 4 data sheet rev. a | page 43 of 99 table 12 . wideband filter noise: performance vs. output data rate (v ref = 4.0 96 v) output data rate (ksps) ?3 db bandwidth (khz) shorted input dynamic range (db) rms noise (v) fast mode 256 110.8 107.96 11.58 128 55.4 111.43 7.77 64 27.7 114.55 5.42 32 13.9 117.58 3.82 16 6.9 120.56 2.72 8 3.5 123.5 1.94 median mode 128 55.4 108.13 11.36 64 27.7 111.62 7.6 32 13.9 114.75 5.3 16 6.9 117.79 3.74 8 3.5 120.8 2.64 4 1.7 123.81 1.87 eco mode 32 13.9 108.19 11.28 16 6.9 111.69 7.54 8 3.5 114.83 5.25 4 1.7 117.26 3.71 2 0.87 120.88 2.62 1 0.43 123.88 1.85 ta ble 13 . sinc5 filter noise: performance vs. output data rate (v ref = 4.096 v) output data rate (ksps) ?3 db bandwidth (khz) shorted input dynamic range (db) rms noise (v) fast mode 256 52.224 111.36 7.83 128 26.112 114.55 5.43 64 13.056 117.61 3.82 32 6.528 120.61 2.71 16 3.264 123.52 1.93 8 1.632 126.39 1.39 median mode 128 26.112 111.53 7 .68 64 13.056 114.75 5.3 32 6.528 117.81 3.72 16 3.264 120.82 2.64 8 1.632 123.82 1.87 4 0.816 126.79 1.33 eco mode 32 6.528 111.57 7.65 16 3.264 114.82 5.26 8 1.632 117.88 3.7 4 0.816 120.9 2.61 2 0.408 123.91 1.85 1 0.204 126.89 1.31
ad7768/ad7768 - 4 data sheet rev. a | page 44 of 99 ap plications i n formation the ad7768 / ad7768 - 4 offer users a multichannel platform measurement solution for ac and dc signal processing. flexible filtering allows the ad7768 / ad7768 - 4 to be config - ured to simultaneously sample ac and dc sign als on a per channel basis. power scaling allows users to trade off the input bandwidth of the measurement vs . the current consumption. this ability , coupled with the flexibility of the digital filtering , allows the user to optimize the energy efficiency o f the measurement , while still meeting power, bandwidth, and performance targets. key capabilities that allow users to choose the ad7768 / ad7768 - 4 as their platform high resolution adc are highlighted as follows: ? eight fully differential or pseudo differential analog inputs on the ad7768 (four channels on th e ad7768 - 4 ) . ? f ast throughput sim ultaneous sampling adcs catering for input signals up to 110.8 kh z . ? three selectable power modes ( fast , median , and eco ) for scaling the current consumpti on and input bandwidth of the adc for optimal measurement efficiency . ? a nalog input precharge and reference precharge buffers reduce the drive requirements of external amplifiers. ? control of reference and analog input precharge buffers on a per channel basi s . ? wideband , low ripple , digital filter for ac measurement . ? fast s inc5 filter for precision low frequency measurement . ? t wo channel modes, defined by the user selected filter choice , and decimation ratios, can be defined for use on different adc channels . t his enables optimization of the input bandwidth versus the signal of interest. ? option of spi or pin strapped control and configuration. ? offset, gain, and phase calibration register s per channel. ? common - mode voltage output buffer for use by driver amplif ie r. ? on - board avdd2 and iovdd ldos for the low power, 1.8 v , internal circuitry . refer to figure 73 and table 14 for the typical connections and minimum requirements to get s tarted using the ad7768 / ad7768 - 4 . table 15 shows the typical power and performance of the ad7768 / ad7768 - 4 for the available power modes , for each filter type . 14001-077 adc data serial interface spi control interface v out v in v in adr4540 avdd1a, avdd1b avss avdd2a, avdd2b regcapa, regcapb precharge buffers ain7+* ain7?* ain0+ ain0? vcm ad7768/ad7768-4 dregcap iovdd refx+ refx? 5v ada4940-1/ ada4940-2 24-bit ? adc sinc5 low latency filter wideband low ripple filter sync_in drdy sync_out start reset formatx dclk dout6*, din dout7* st0/cs st1 * /sclk dec0/sdo dec1/sdi filter/gpio4 mode3/gpio3 to mode0/gpio0 xtal2/mclk xtal1 pin/spi dout0 dout1 dout2 dout3 dout4* dout5* ada4841-1 ? + *these pins exist only on the ad7768. suggested op amps: fast mode: ada4896-2 or ada4807-2 median mode: ada4940-2 or ada4807-2 eco mode: ada4805-2 figure 73 . typical c onnection d iagram
data sheet ad7768/ad7768 -4 rev. a | page 45 of 99 table 14. requirements to operate the ad7768 / ad7768-4 requirement description power supplies 5 v avdd1 supply, 2.25 v to 5 v avdd2 supply, 1.8 v or 2.5 v to 3.3 v iovdd supply ( adp7104 / adp7118 ) external reference 2.5 v, 4.096 v, or 5 v ( adr4525 , adr4540 , or adr4550 ) external driver amplifier s the ada4896-2 , the ada4940-1 / ada4940-2 , the ada4805-2 , and the ada4807-2 external clock crystal or a cmos/lvds clock for the adc modulator sampling fpga or dsp input/output voltage of 2.5 v to 3.6 v, or 1.8 v (see the 1.8 v iovdd operation section) table 15 . speed, dynamic range, thd, and power overview; eight channels active, decimate by 32 1 power mode output data rate (ksps) thd (db) sinc5 filt er wideband filter dynamic range (db) bandwidth (khz) power dissipation (mw per channel) dynamic range (db) bandwidth (khz) power dissipation (mw per channel) fast 256 ?11 5 111 52.224 41 108 110.8 52 median 128 ?120 111 2 6.112 22 108 55.4 28 eco 32 ?120 111 6.528 8.5 108 13.9 9.5 1 analog precharge buffer s on, reference precharge buffer s and vcm disabled, typical values, avdd1 = 5 v, avdd2 = iovdd = 2.5 v, v ref = 4.096 v , mclk = 32.768 mhz, dclk = mclk/4, t a = 25c. power supplies the ad7768 / ad7768 -4 ha ve three independent power supplies : avdd1 (avdd1a and avdd2a), avdd2 (avdd2a and avdd2b), and iovdd . the reference potentials for these supplies are avss and dgnd. tie a ll the avss supply pins (avss1a, avss1b, avss2a, avss2b, and avss) to the same potential with respect to dgnd. avdd1a, avdd1b, avdd2a, and avdd2b are referenced to this avss rail . iovdd is referen ced to dgnd. the supplies can be powered within the following ranges: ? avdd1 = 5 v 10% , relative to avss ? avdd2 = 2 v to 5.5 v, relative to avss ? iovdd (with internal regulator) = 2.25 v to 3.6 v, relative to dgnd ? io vdd (bypassing regulator) = 1.72 v to 1. 88 v, relative to dgnd ? avss = ?2.75 v to 0 v, relative to dgnd the avdd1 a and avdd1b ( av dd 1 ) suppl ies power the analog front end, reference input , and common - mode output circuitry. avdd1 is referenced to avss , and all avdd1 supplies must be tied to the same potential with respect to av ss. if avdd1 supplies are used in a 2.5 v split supply configuration, the adc inp uts are truly bipolar . when using split supplies, reference the absolute maximum ratings , which apply to the voltage allowed between a vss and iovdd supplies. the avdd2 a and a vdd2b (avdd2) suppl ies connect to internal 1.8 v analog ldo regulator s . th e regulator s power the adc core. avdd2 is referenced to avs s , and all avdd2 supplies must be tied to the same potential with respect to avss . the voltage on avdd2 can range from 2 v (minimum) to 5.5 v (maximum) , with respect to avss . iovdd powers the internal 1.8 v digital ldo regulator. this regulator powers the digital logic of the adc. iovdd also sets the voltage levels for the spi interface of the adc. iovdd is refer enced to dgn d, and the v oltage on iovdd can vary from 2.25 v (minimum) to 3.6 v (maximum) , with respect to dgnd . iovdd can also be configured to run at 1.8 v . in this case , iovdd and dregcap must be tied together and must be within the range of 1.72 v (minimum) to 1. 88 v (maximum) , with respect to dgnd. s ee the 1.8 v iovdd operation section for more information on operating the ad7768 / ad7768 -4 at 1.8 v iovdd . recommended power supply configuration analog devices, inc., has a wide range of power management products to meet the requirements of most high performance signal chains. an example of a power solution that us es the adp7118 is shown in figure 74. t he adp7118 provides positive supply rails for optimal converter performance, creating either a single 5 v, 3.3 v, or dual avdd1 x and avdd2 x/ iovdd, depending on the required supply configuration. the adp7118 c an operate from input voltages of up to 20 v. adp7118 ldo 12v input 5v: a vdd1x 3.3 v: a vdd2x/iovdd adp7118 ldo 14001-078 figure 74 . power s upply c onfiguration alternatively, the adp7112 or adp7104 can be selected for powering the ad7768 / ad7768 -4 . refer to the an - 1120 applicatio n note for more information regarding low noise ldo performance and power supply filtering.
ad7768/ad7768 - 4 data sheet rev. a | page 46 of 99 1.8 v iovdd operation the ad7768 / ad7768 - 4 contain an internal 1.8 v ldo on the iovdd supply to regulate the iovdd down to the operatin g voltage of the digital core. this internal ldo allows the internal logic to operate efficiently at 1.8 v and the input/output logic to operate at the level set by iovdd. the iovdd supply is rated from 2.25 v to 3.6 v for normal operation, and 1.8 v for ldo bypass setup. 14001-306 37 start 36 sync_in 35 iovdd 34 dregcap 33 dgnd 38 sync_out 28 dclk 29 drdy 30 reset 31 xtal1 32 xtal2/mclk 1.8v iovdd supply figure 75 . dregcap and iovdd connection diagram for 1.8 v iovdd operation users can bypass the ldo by shorting the dregcap pin to iovdd (see figure 75 ), which pulls the internal ldo out of regulation and sets the internal core voltage and input/output logic levels to the iovdd level. when bypassing the internal ldo, the maximum operating voltage of the iovdd supply is equal to the maximum operating voltage of the internal digital core, wh ich is 1.72 v to 1.88 v. there are a number of performance differences to consider when o perating at 1.8 v iovdd. see the 1.8 v iovdd specifications section for detailed specifications while operating at 1.8 v iov dd. analog supply internal connectivity the ad7768 / ad7768 - 4 have two analog supply rails, avdd1 and avdd2, which are both referred to avss. these supplies are completely separate from the digital pins iovdd, dregcap, and dgnd. to achieve optimal p erformance and isolation of the adcs, more than one device pin supplies these analog rails to the internal adcs. ? avss1a (pin 3) and avss2a (pin 62) are internally connected. ? avss (pin 54) is connected to the substrate, and is connected i nternally to avss1 b (pin 46) and avss2b (pin 51). ? the following supply and reference input pins are sep arate on chip: avdd1a, avdd1b, avdd2a, avdd2b, ref1+, ref1?, ref2+, and ref2?. ? on the ad7768 - 4 , the following avss pins are separate on chip: pin 7, pin 8, pin 9, pin 10, pin 39, pin 40, pin 41, and pin 42. the details of which individual supplies are shorted internally are given in this section for information purposes. in general, connect the supplie s as described in the power supplies section. device configuration the ad7768 / ad7768 - 4 ha ve independent paths for reading data from the adc conversions and for controlling the device functionality. for control, the device can be configured in either of two m odes . the two modes of configurat ion are ? pin control mode: pin strapped digital logic inputs (which allows a subset of the configurability options) ? spi control mode : o ver a 3 - wire or 4 - wire spi interface ( c omplete configurability) on power - up, the state of the pin /spi p in determines the mode used. immediately after power - up , the user must apply a soft or hard reset to the device when usi ng either control mode. interface data format when operating the device, the data format of the serial inter - face is determined by the f ormat0 and format1 pin settings on the ad7768 , or the format0 pin on the ad7768 - 4 . table 31 show s that each adc can be assigned a dout x pin, or , alternatively, the data can be arranged to shar e the dout x p ins in a time division multiplexed manner . for m ore detail s, see the data interface section. pin control pin control m ode eliminates the need for a n spi communication interface . when a single known configuration i s required by the user , or when only limited reconfiguration is required, the number of signals that require routing to the digital host can be reduced using this mode . pin control mode is useful in digitally isola ted applications where minimal adjustment of the configuration is needed. pin control offers a subset of the core functionality and ensures a known state of operation after power - up, reset, or a fault condition on the power supply. in pin control mode , the analog input precharge buffers are enable d by default for best performance. the reference input precharge buffers are disabled in pin control mode. after any change to the configuration in pin control mode , the user must provide a sync signal to the ad7768 / ad7768 - 4 by applying the appropriate pulse to the start pin or sync_in pin to ensure that the configuration changes are applied correctly to the adc and digital filters. setting the filter t he filter function chooses between the two filter settings. in pin control mode , all adc channel s use the same filter type, which is selected by the filter pin, as shown in table 16. table 16 . filter control pin logic level function 1 sinc5 filter selected 0 wideband filter selected
data sheet ad7768/ad7768-4 rev. a | page 47 of 99 setting the decimation rate pin control mode allows selection from four possible decimation rates. the decimation rate is selected via the dec1 and dec0 pins. the chosen decimation rate is used on all adc channels. table 17 shows the truth table for the decx pins. table 17. decimation rate control pins truth table dec1 dec0 decimation rate 0 0 32 0 1 64 1 0 128 1 1 1024 operating mode the mode3 to mode0 pins determine the configuration of all channels when using pin control mode. the variables controlled by the modex pins are shown in table 18. the user selects how much current the device consumes, the sampling speed of the adc (power mode), how fast the adc result is received by the digital host (dclk_div), and how the adc conversion is initiated (conversion operation). figure 76 illustrates the inputs used to configure the ad7768 in pin control mode, and figure 77 illustrates the inputs used to configure the ad7768-4 in pin control mode. table 18. modex pins: variables for control control variable possible settings sampling speed/power consumption power mode fast median eco data clock output frequency (dclk_div) dclk = mclk/1 dclk = mclk/2 dclk = mclk/4 dclk = mclk/8 conversion operation standard conversion one-shot conversion the modex pins map to 16 distinct settings. the settings are selected to optimize the use cases of the ad7768 / ad7768-4 , allowing the user to reduce the dclk frequency for lower, less demanding power modes and selecting either the one-shot or standard conversion modes. see table 20 for the complete selection of operating modes that are available via the modex pins in pin control mode. the power mode setting automatically scales the bias currents of the adc and divides the applied mclk signal to the correct setting for that mode. note that this is not the same as using spi control, where separate bit fields exist to control the bias currents of the adc and mclk division. in pin control mode, the modulator rate is fixed for each power mode to achieve the best performance. table 19 shows the modulator division for each power mode. table 19. modulator rate, pin control mode power mode modulator rate, f mod fast mclk/4 median mclk/8 eco mclk/32 diagnostics pin control mode offers a subset of diagnostics features. internal errors are reported in the status header output with the data conversion results for each channel. internal crc errors, memory map flipped bits, and external clocks not detected are reported by bit 7 of the status header and indicate that a reset is required. the status header also reports filter not settled, filter type, and filter saturated signals. users can determine when to ignore data by monitoring these error flags. for more information on the status header, see the adc conversion output: header and data section. pin control mode pin/spi = low option to select between filters to dsp/ fpga channel standby ch 0 to ch 3 standby ch 4 to ch 7 standby output data format 1 channel per pin 4 channels per pin 8 channels per pin decimation rates /32 /64 /128 /1024 mode configuration mode 0x0 to mode 0xf set up via 4 pins dec0/ dec1 filter dout7 dout1 dout0 format1 format0 st1 ad7768 st0 pin/spi mode0 mode1 mode2 mode3 14001-079 figure 76. ad7768 pin configurable functions
ad7768/ad7768-4 data sheet rev. a | page 48 of 99 pin control mode pin/spi = low option to select between filters to dsp/ fpga channel standby ch 0 to ch 3 standby output data format 1 channel per pin 4 channels per pin decimation rates /32 /64 /128 /1024 mode configuration mode 0x0 to mode 0xf set up via 4 pins dec0/ dec1 filter format0 ad7768-4 st0 pin/spi mode0 mode1 mode2 mode3 dout0 dout1 dout2 dout3 14001-300 figure 77. ad7768-4 pin configurable functions table 20. modex selection details: pin control mode mode hex. mode3 mode2 mode1 mode0 power mode dclk frequency data conversion 0x0 0 0 0 0 eco mclk/1 standard 0x1 0 0 0 1 eco mclk/2 standard 0x2 0 0 1 0 eco mclk/4 standard 0x3 0 0 1 1 eco mclk/8 standard 0x4 0 1 0 0 median mclk/1 standard 0x5 0 1 0 1 median mclk/2 standard 0x6 0 1 1 0 median mclk/4 standard 0x7 0 1 1 1 median mclk/8 standard 0x8 1 0 0 0 fast mclk/1 standard 0x9 1 0 0 1 fast mclk/2 standard 0xa 1 0 1 0 fast mclk/4 standard 0xb 1 0 1 1 fast mclk/8 standard 0xc 1 1 0 0 eco mclk/1 one-shot 0xd 1 1 0 1 median mclk/1 one-shot 0xe 1 1 1 0 fast mclk/2 one-shot 0xf 1 1 1 1 fast mclk/1 one-shot configuration example in the example shown in table 23, the lowest current consumption is used, and the ad7768/ ad7768-4 are connected to an fpga. the formatx pins are set such that all eight data outputs, dout0 to dout7, connect to the fpga. for the lowest power, the lowest dclk frequency is used. the input bandwidth is set through the combination of selecting decimation by 64 and selecting the wideband filter. odr = f mod decimation ratio where: mclk = 32.768 mhz. f mod is mclk/32 for eco mode (see table 19). decimation ratio = 64. thus, for this example, where mclk = 32.768 mhz, odr = (32.768 mhz/32) 64 = 16 khz minimizing the dclk frequency means selecting dclk = mclk/8, which results in a 4 mhz dclk signal. the period of dclk in this case is 1/4 mhz = 250 ns. the data conversion on each doutx pin is 32 bits long. the conversion data takes 32 250 ns = 8 s to be output. all 32 bits must be output within the odr period of 1/16 khz, which is approximately 64 s. in this case, the 8 s required to read out the conversion data is well within the 64 s between conversion outputs. therefore, this combination, which is summarized in table 23, is viable for use.
data sheet ad7768 /ad7768 - 4 rev. a | page 49 of 99 channel standby t able 21 and table 23 show how the user can put channels into standby mode. set either st0 or st1 to logic 1 to place banks of four channels into standby mode. when in standby mode , the channels are disabled but st ill hold their position in the output data stream . the 8 - bit header and 24 - bit conversion result are set to all zero s when the adc channels are set to standby . the vcm voltage output is associated with the channel 0 circuitry. if channel 0 is put into stan dby mode, the vcm voltage output is also disabled for maximum power savings. channel 0 must be enabled while vcm is being used externally to the ad7768 / ad7768 - 4 . the crystal excitation circuitry is associated with the channel 4 (channel 2 on the ad7768 - 4 ) circuitry. if channel 4 (channel 2 on the ad7768 - 4 ) is put into standby mode, the crystal circuitry is also disabled for maximum power savings. channel 4 must be enabled while the external crystal is used on the ad7768 . channel 2 must be enabled while the external crystal is used on the ad7768 - 4 . table 21. truth table for the ad7768 st0 and st1 p ins st1 st0 function 0 0 all channels operational . 0 1 channel 0 to channel 3 in standby. channel 4 to c hannel 7 operational. 1 0 channel 4 to channel 7 in standby. c hannel 0 to channel 3 operational . 1 1 all channels in standby . table 22 . truth table for the ad7768 -4 st0 pin st0 function 0 all channels operational. 1 c hannel 0 to channel 3 in standby. spi con trol the ad7768 / ad7768 - 4 ha ve a 4 - wire spi interface that is compatible with qspi?, microwire?, and dsps. the interface operates in spi mode 0 . in spi mode 0, sclk idles low, the falling edge of cs clocks out the msb, the falling edge of sclk is the drive edge, and the rising edge of sclk is the sample edge. this means that data is clocked out on the falling/drive edge and data is clocked in on the rising/sample edge. drive edge sample edge 14001-080 figure 78 . spi mode 0 sclk edges accessing the adc register map to use spi c ontrol mode, set the pin /spi pin to logic high . the spi control operates as a 16 - bit , 4 - wire interface , allowing read and write access. figure 80 shows the interface format between the ad7768 / ad7768 - 4 and the digital host. the spi serial control interface of the ad7768 is an independent p ath for controlling and monitoring the ad7768 . there is no direct link to the data interface. the timing of mclk and dclk is not directly related to the timing of the spi control interface. however, the user must ensure that the spi reads and writes satisfy the minimum t 30 specification (see table 4 and table 6 ) so that the ad7768 / ad7768 - 4 can detect changes to the register map. spi access is ignored during the period immediately after a reset. allow the full adc start - up time after reset (see table 1 ) to elapse before accessing the ad7768 / ad7768 - 4 over the spi interface. table 23. modex example selection mode hex mode3 mode2 mode1 mode0 power mode dclk frequency data conversion 0x3 0 0 1 1 eco mclk/8 standard
ad7768/ad7768-4 data sheet rev. a | page 50 of 99 spi interface details each spi access frame is 16 bits long. the msb (bit 15) of the sdi command is the r/ w bit; 1 = read and 0 = write. bits[14:8] of the sdi command are the address bits. the spi control interface uses an off frame protocol. this means that the master (fpga/dsp) communicates with the ad7768/ ad7768-4 in two frames. the first frame sends a 16-bit instruction (r/ w , address, and data) and the second frame is the response where the ad7768/ ad7768-4 send 16 bits back to the master. during the master write command, the sdo output contains eight leading zeros, followed by eight bits of data, as shown in figure 80. figure 79 illustrates the off frame protocol. register access responses are always offset by one cs frame. in figure 79, the response (read resp 1) to the first command (cmd 1) is output by the ad7768/ ad7768-4 during the following cs frame at the same time as the second command (cmd 2) is being sent. sclk sdi sdo cs cmd 1 cmd 2 read resp 1 14001-082 figure 79. off frame protocol spi control interface error handling the ad7768 / ad7768-4 spi control interface detects whether it has received an illegal command. an illegal command is a write to a read only register, a write to a register address that does not exist, or a read from a register address that does not exist. if any of these illegal commands are received by the ad7768/ ad7768-4 , the ad7768/ ad7768-4 responds with an error output of 0x0e00. spi reset configuration after a power-on or reset, the ad7768 / ad7768-4 default configuration is set to the following low current consumption settings: ? eco power mode with f mod = mclk/32. ? interface configuration of dclk = mclk/8, header output enabled, and crc disabled. ? filter configuration of channel mode a and channel mode b is set to sinc5 and decimation = 1024. ? channel mode select is set to 0x00, and all channels are assigned to channel mode a. ? the analog input precharge buffers are enabled and the reference precharge buffers are disabled on all channels. ? the offset, gain, and phase calibration are set to the zero position. ? continuous conversion mode is enabled. spi control functionality spi control offers the superset of flexibility and diagnostics to the user. the following sections highlight the functionality and diagnostics offered when spi control is used. after any change to these configuration register settings, the user must provide a sync signal to the ad7768 / ad7768-4 through either the spi_sync command, or by applying the appropriate pulse to the start pin or sync_in pin to ensure that the configuration changes are applied correctly to the adc and digital filters. channel configuration the ad7768 has eight fully differential analog input channels. the ad7768-4 has four fully differential analog input channels. the channel configuration registers allow the channel to be individually configured to adapt to the measurement required on that channel. channels can be enabled or disabled using the channel standby register, register 0x00. analog input and reference precharge buffers can be assigned per input terminal. gain, offset, and phase calibration can be controlled on a per channel basis using the calibration registers. see the per channel calibration gain, offset, and sync phase section for more information. sclk sdi d0 d1 d2d3d4d5d6d7a0a1a2a3a4a5a6 r/w sdo d0 d1d2d3d4d5d6d7 00000000 cs 14001-081 figure 80. write/read command
data sheet ad7768 /ad7768 - 4 rev. a | page 51 of 99 channel modes in spi control mode, the user can set up two ch annel modes, channel mode a (register 0x01), and channel mode b (register 0x02). each channel mode register can have a specific filter type and decimation ratio. using the channel mode select register (register 0x03), the user can assign each channel to ei ther channel mode a or channel mode b , which maps that mode to the required adc channel s . these modes allow different filter types and decimation rates to be selected and mapped to any of the adc channels. when different decimation rates are selected on di fferent channels , the ad7768 / ad7768 - 4 output a data ready signal at the fastest selected decimation rate. any channel that runs at a lower output data rate is updated only at that slower rate. in between valid result data, the data for that channe l is set to zero and the repeated data bit is set in the header status bits to distinguish it from a real conversion result (see the adc conversion output: header and data section). on the ad7768 , consider channel mode a as the primary group. in this respect, it is recommend ed that there always be at least one channel assigned to channel mode a. if all eight channels of the ad7768 are assigned to channel mode b , conversion data is not output on the data interface for any of the channels. this consideration does not affect the ad7768 - 4 . on the ad7768 - 4 , it is recommended that channel mode a be set to the s inc5 filter whenever possible. there is a small power saving in iovdd current when channel mode a is set to the s inc5 filter compared to setting channel mode a to the w ideband filter. for example, to assign two channels of the ad7768 - 4 to the wideband filter, and the remaining two channels to the s inc5 filter , it is recommended to assign the two s inc5 filter channels to channel mode a. set channel mode a to the s inc5 filter, set channel mode b to the wideband filter, and assign the two w ideband filter channels to channel mode b. sim ilarly, to assign all four channels of the ad7768 - 4 to wideband filter, assign all four channels to channel mode b. set channel mode b to the wideband filter, and keep channel mode a set to the s inc5 filter. assigning the channels in this way ensure s that the lowest iovdd current is achieved. table 24 . channel mode a/channel mode b, register 0x01 and register 0x02 bits bit name setting description reset access 3 f ilter_type_x filter output 0x1 rw 0 wideband filter 1 sinc5 filter [2:0] dec_rate_x decimation rate 0x5 rw 000 to 101 32 to 1024 table 25 . channel mode selection, register 0x03 bits bit name setting descriptio n reset access [7:0] ch_x_mode channel x 0x0 rw 0 mode a 1 mode b reset over spi control interface two successive commands must be written to the ad7768 / ad7768 - 4 data control register to initiate a full reset of the device over the spi interface. this action fully resets all registers to the default conditions. details of the commands and their sequence are shown in tabl e 44 for the ad7768 or table 70 for the ad7768 - 4 . after a reset over the spi control interface, the ad7768 / ad7768 - 4 respond to the first command sent to them with 0x0e00 . this response , in addition to the fact that all registers have assumed their default values , indic ates that the software reset succeeded. sleep mode sleep m ode puts the ad7768 / ad7768 - 4 into their lowest power mode. in sleep mode , all adcs are disabled and a l arge portion of the digital core is inactive . the ad7768 / ad7768 - 4 spi remains active and is available to the user when in sleep mode. writ e to r egister 0x04 , bit 7 to exit sleep mode. for the lowest power consumption , select the sinc5 filter before entering sleep mode. channel standby for efficient power usage, u sers can place the selected channel s into standby mode , effectively disabling them, when not in use . setting the bits in r egister 0x00 disa bles the corresponding channel (s ee table 38 for the ad7768 or table 64 for the ad7768 - 4 ) . for maximum power saving s, switch disabled channels to the sinc5 filter using the channel mode configurations , which disable s some clocks associated with the wideband filter s of those channels . for highest p ower savings when disabling channels on the ad7768 - 4 , set channel mode a to the s inc5 filter, and assign the disabled channels to channel mode a , while keeping any active channels in cha nnel mode b. the vcm voltage output is associated with the channel 0 circuitry. if channel 0 is put into standby mode, the vcm voltage output is also disabled for maximum power savings. channel 0 must be enabled while vcm is being used externally to the ad7768 / ad7768 - 4 . the crystal excitation circuitry is associated with the channel 4 (channel 2 on the ad7768 - 4 ) cir cuitry. if channel 4 (channel 2 on the ad7768 - 4 ) is put into standby mode, the crystal circuitry is also disabled for maximum power savings. channel 4 must be enabled while the externa l crystal is used on the ad7768 . channel 2 must be enabled while the external crystal is used on the ad7768 - 4 .
ad7768/ad7768 - 4 data sheet rev. a | page 52 of 99 clocking selections the internal modulator frequency (f mod ) that is used by each of the adcs in the ad7768 / ad7768 - 4 is derived from the externally applied mclk signal. the mclk division bits allow the user to control the ratio between the mclk frequency and the internal modulator clock frequency. this control allows the user to select the division ratio that is best for their configuration. the appropriate clock configuration depends on the p ower m ode, the d ecimation rate , and the b ase mclk frequency available in the system. see the clocking, sampling tree section for further info rmation on setting mclk _ div correctly. mclk s ource s election the following clocking options are available as the mclk input source in spi control mode: ? lvds ? external crystal ? cmos input mclk setting clk_sel to logic low configures the ad7768 / ad7768 - 4 for correct operation using a cmos clock . setting clk _sel to logic high enables the use of an external crystal. if clk_sel is set to logic high and b it 3 of r egister 0x04 is also set, the applic ation of an lvds clock signal to the mclk pin is enabled . lvds clocking is exclusive to spi control mode and requires the register selec tion for operation (s ee table 42 for the ad7768 or table 68 for the ad7768 - 4 ). the dclk rate is derived from mclk. dclk division (the ratio between mclk and dclk) is controlled in the interface configuration selection register , register 0x07 (s ee tabl e 45 for the ad7768 or table 71 for the ad7768 - 4 ) . interface configuration the data interface is a master output interface, where adc conversion result s are output by the ad7768 / ad7768 - 4 at a rate based on the mode selected. the interface consists of a data clock (dclk) , the data ready ( drdy ) framing output , and the data output pins (dout0 to dout7 for the ad7768 , dout0 to dout3 for the ad7768 - 4 ) . on the ad7768 , t he interface can be configured to output conversion data o n one, two, or eight of the doutx pins. the doutx configuration for the ad7768 is selected using the formatx pins (see table 31). on the ad7768 - 4 , the interface can be configured to output conversion data on one or four of the doutx pins. the doutx configuration for the ad7768 - 4 is selected using the format0 pin (see table 32 ). the dclk rate is a direct division of the mclk input and can be controlled using bits[1:0] of register 0x07. the minimum dclk rate can be calculated as dclk (min imum ) = output data rate channels per doutx 32 bits where mclk dclk . with eight adc s enabled, an mclk rate of 32 .768 mhz, an odr of 25 6 ksps, and two doutx channels , dclk ( minimum ) is 256 ksps 4 channels per doutx 32 bits = 32 .768 mhz where dclk = mclk /1. for more information on the status header, crc, and interface configuration , see the data interface section. crc protection the ad7768 / ad7768 - 4 can be configured to output a crc message per channel every 4 or 16 samples. this function is available only with spi control. crc is enabled in the interface contr ol register , register 0x07 (s ee the crc check on data interface section ) . adc synchronization o ver spi the adc synchronization over spi allows the user to request a synchronization pulse to the adcs over the spi in terface. to initiate the synchronization in this manner , write to b it 7 in r egister 0x06 twice. first , the user must writ e a 0, which sets sync_out low, and then write a 1 to set the sync_out logic high again. the spi_ sync command is recognized after the last rising edg e of sclk in the spi instruction , where the spi_sync bit is changed from low to high. the spi_sync command is then output synchro - nous ly to the ad7768 / ad7768 - 4 mclk signal on the s ync_out pin. the user must connect th e sync_out signal to the sync_in pin on the pcb . 14001-301 start sync_in doutx drdy mclk spi interface sync_out dsp/ fpga ad7768/ ad7768-4 synchronization logic digital filter master clock iovdd figure 81 . connection diagram for synchronization using spi_sync the sync_out pin can also be routed to the sync_in pins of other a d7768 / ad7768 - 4 device s, allowing simultaneous sampling to occur across larger channel count systems. any daisy - chained system of ad7768 / ad7768 - 4 devices requires t hat all adc s be synchronized. in a daisy - chained system of ad7768 / ad7768 - 4 devices, two successive synchronization pulses must be applied to guarantee that all adcs are synchronized. two synchronization pulses are also required in a system of more than one ad7768 / ad7768 - 4 device sharing a single mclk signal, where the drdy pin of only one device is used to detect new data.
data sheet ad7768 /ad7768 - 4 rev. a | page 53 of 99 as per any synchronization pulse present on the sync_in pin, the digital filters of the ad7768 / ad7768 - 4 are reset by the spi_sync command . the full settling time of the filters must then elapse before valid data is output on the data interface. analog input precharge buffers the ad7768 / ad7768 - 4 contain precharge buffers on each analog input to ease t he drive requirements on t he external amplifier. each analo g i nput precharge buffer can be ena bled or disabled using the analog i nput precharge buffer registers (s ee table 52 and table 53 for the ad7768 or tabl e 78 and table 79 for the ad7768 - 4 ) . reference precharge buffers the ad7768 / ad7768 - 4 contain r eference precharge buffers on each reference input to ease the drive requirements on the external reference an d help to settle any nonlinearity on the reference inputs. ea ch reference precharge buffer can be ena bled or disabled using the reference precharg e buffer registers (s ee table 54 and table 55 for the ad7768 or table 80 and table 81 for the ad7768 - 4 ) . per channel calibration gain, offset , and s ync phase the user can adjust the gain, offset , and sync phase of the ad7768 / ad7768 - 4 . these options are available only in spi control mode. further register information and cali bration instructions are available in the offset registers section , the gain registers section , and the sync phase offset registers section . see the calibration section for information on calibration equations. gpio s the ad7768 / ad7768 - 4 ha ve five general - purpose input/output ( gpio ) pins available when operating in spi control mode. f or f urther i nfor mation on gpio configuration , see the gpio functionality section. spi control mode extra diagnostic features ram built in self test the ram built in self test (bist) is a coefficient check for the d igital filters. the ad7768 / ad7768 - 4 dsp path uses some internal memories f or storing data associated with filtering and calibration. a user may, if desired, initiate a built in self test (bist) of these memories. normal conversions are not possi ble while bist is running. the test is started by writing to the bist control register, register 0x08 . the results and status of the test are available in the s tatus register, register 0x09 (s ee table 47 for the ad7768 or table 73 fo r the ad7768 - 4 ) . normal adc conversion is disrupted when this test is run. a synchronization pulse is required after this test is complete to resume normal adc operation. revision identi fication number the ad7768 / ad7768 - 4 contain an identification register that can be accessed in spi control mode , the revision identification register . th is registe r i s an excellent way to ve rify the correct operation of the serial control interfac e. register information is available in the revision identification register section. diagnostic meter mode the d iagnostic metering mode can be used to verify the functionality of each adc by internally passing a p ositive full - scale , m idscale , or negative full - scale voltage to the adc . the user can then read the resulting adc conversion result to determine that the adc is operating correctly . t o configure adc conversion diagnostics , see the adc diagnostic receive select register section and the adc diagnostic control register section .
ad7768/ad7768 - 4 data sheet rev. a | page 54 of 99 circuit information core signal chain each adc channel on the ad7768 / ad7768 - 4 has an id entical signal path from the analog input pins to the data interface . figure 83 shows a top level implementation of th e core signal chain . each adc channel has its own - modulator that oversamples the analog inpu t and passes the digital representation to the digital filter block. the modulator sampling frequency (f mod ) ranges are explained in the clocking, sampling tree, and power scaling section. the data is filtered, sca led for gain and offset (depending on user setting s) , and then output on the data interface. control of the flexible settings for the signal chain is provided by either using the pin control or the spi control set at power - up by the state of the pin /spi input pin. the ad7768 / ad7768 - 4 can use up to a 5 v reference and converts the differential voltage between the analog inputs (ain x + and ain x ?) into a digital output. the analog inputs can be configured as either differential or pseudo differential inputs. as a pseudo differential input, either ainx+ or ainx ? can be connected to a constant input voltage (such as 0 v , gnd , avss , or some other re ference voltage). the adc convert s the voltage difference between the analog input pins into a digital code on the output. using a common - mode voltage of avdd1 /2 for the analog inputs , ain x + and ain x ? , maximizes the adc input range. the 24 - bit conversion r esult is in twos complement , msb first, format. figure 82 shows the ideal transfer functions for the ad7768 / ad7768 - 4 . adc power mode s the ad7768 / ad7768 - 4 ha ve three selectable power modes. in pin control mode, the modulator rate and power mode are tied together for best performance. in spi control mode, the user can select the power mode and modulator mclk divider setting s. the choice of power modes gives more flexibility to control the bandwidth a nd power dissipation for the ad7768 / ad7768 - 4 . table 11 shows the recommended f mod frequencies for each power mode , and table 42 shows the register information for the ad7768 , and tabl e 68 shows the register information for the ad7768 - 4 . 10 0 .. . 0 00 10 0 .. . 0 01 10 0 .. . 0 10 01 1 .. . 1 01 01 1 .. . 1 10 01 1 .. . 1 11 adc code (twos complement) an al og input +fs ? 1.5lsb +fs ? 1lsb ?fs + 1lsb ?fs ?fs + 0.5lsb 14001-083 figure 82 . adc ideal transfer functions (fs is full scale) table 26. output code s and ideal input voltages description analog input ( ainx+ ? ( ainx? ) ) v ref = 4.096 v digital output code , twos complement (hex . ) fs ? 1 lsb +4. 095999512 v 0x7fffff midscale + 1 lsb + 488 nv 0x000001 midscale 0 v 0x000000 midscale ? 1 lsb ? 488 nv 0xff ffff ?fs + 1 lsb ?4. 095999512 v 0x800001 ?fs ? 4.096 v 0x800000 digi t al fi l ter dclk pin/spi drd y doutx ainx+ ainx? fi l ter/gpio4 cs sclk sdo sdi mode3/gpio3 t o mode0/gpio0 contro l block pin contro l spi contro l dat a inter f ace contro l - modulator precharge buffer esd protection control option pin or spi signal chain for single channel mclk st art sync_out sync_in reset 14001-182 figure 83 . top level core signal chain and control
data sheet ad7768 /ad7768 - 4 rev. a | page 55 of 99 analog inputs figure 84 shows the ad7768 / ad7768 - 4 anal og front end. t he esd protection diodes that are designed to protect the adc from some short duration overvoltage and esd events are shown on the signal path . the analog input is sampled at twice the modulator sampling frequency, f mod , which is derived fro m mclk. by default, t he a dc internal sampling capacitor s, cs1 and cs2 , are driven by a per channel analog input precharge buffer to ease the driving requirement o f the external network . bps 0+ a vdd1 ain0+ cs2 phi 0 phi 1 phi 1 phi 0 cs1 ain0? a vss a vss a vdd1 bps 0? 14001-084 figure 84 . analog front end the analog inp ut precharge buffer s provide the initial rough charging of the switched cap acitor network for 25% of the sampling phase. during this first phase , the bypass switches , bps 0+ and bps 0 ?, remain open. for the remaining 75% of the sampling phase, the bypass switches are closed, and the fine accuracy settling charge is provided by the external source. phi 0 and phi 1 represent the modulator clock sampling phases that switch the input signa ls onto the sampling cap acitors, cs1 and cs2. the analog input precharge buffer s reduce the switching kickback from the sampling stage to the external circuitry. the precharge buffer reduces the average input current by a factor of eight , and makes the inp ut cu rrent more signal independent, to reduce the effects of sampling distortion. this reduction in drive requirements allow s pairing of the ad7768 / ad7768 - 4 with lower power , lower bandwidth front end driver amplifiers such as the ada4940 - 1 / ada4940 - 2 . ?400 ?300 ?200 ?100 0 100 200 300 400 0 1 2 3 4 5 6 a in (a) input vo lt age (v diff ) 14001-191 unbuffered ainx+ unbuffered ainx? figure 85 . analog input current (a in ) vs. input voltage , analog input precharge buffer off, v cm = 2.5 v , f mod = 8.192 mhz ?30 ?25 ?20 ?15 ?10 ?5 0 0 1 2 3 4 a in (a) input voltage (v diff ) 14001-192 precharge buffered ainx+ precharge buffered ainx? figure 86 . analog input current (a in ) vs. input voltage , analog input precharge buffer on, v cm = 2.5 v , f mod = 8.192 mhz the analog input precharge buffers can be turned on/off by means of a register w rite to register 0x11 and register 0x12 (pre c harge buffer register 1 and precharge buffer register 2). each analog input precharge buff er is selectable per channel. in pin control mode , the analog input p recharge buffers are always enabled f or optimum performance. when the analog input precharge buffers are disabled , the analog input current is sourced completely from the analog input source. the unbuffered analog input current is calculated from two components : the differential input voltage on the analog input pair , and the analog input voltage with respect to avss . with the precharge buffers disabled, f or 32 .768 mhz mclk in fast mode with f mod = mclk/4 , the differential input current is approximately 4 8 a/v and the current with respect to ground is approximately 17 a / v. for example, if the p recharge buffer s are off , with ain 1 += 5 v, and ain 1 ? = 0 v , estimate the current in each input pin as follows : ain 1 + = 5 v 4 8 a/v + 5 v 17 a/v = 32 5 a ain 1 ? = ? 5 v 4 8 a/v + 0 v 17 a/v = ? 2 4 0 a when the precharge buffers are enabled, the absolute voltage with respect to avss determines the majority of the current. the maximum input current of approximately ? 25 a is measured when the analog input is close to either the avdd1 or avs s rail s . with either precharge buffers enabled or disabled , the analog input current scales linearly with the modulator clock rate. the analog input current versus input voltage is shown in figure 85 . full settling of the analog inputs to the adc require s the use of an external amplifier. pair a mplifiers such as the ada4805 - 2 for eco mode, the ada4807 - 2 or ada4940 - 1 / ada4940 - 2 for median mode , and t he ada4807 - 2 or ada4896 - 2 for fast mode with the ad7768 / ad7768 - 4 (see table 27 for details). running the ad7768 / ad7768 - 4 in median and eco modes or reducing the mclk rate reduces the load and speed requirements of the amplifier ; therefore, lower power amplifiers can be paired with the analog inputs to achieve the optimum signal chain efficiency.
ad7768/ad7768 - 4 data sheet rev. a | page 56 of 99 table 27 . amplifier pairing options power mode amplifier amplifier power (mw/channel) 1 analog input precharge buffer total power ( amplifier + ad7768 ) (mw/channel) 1 fast ada4896 -2 40.6 on 92.1 fast ada4807 - 2 13.6 on 65.1 media n ada4805 - 2 7.5 on 3 5.0 eco ada4805 -2 7.525 on 16.9 1 typical power at 25c. vcm the ad7768 / ad7768 - 4 provide a buffered common - mode voltage output on p in 59. this output can bias up analog input signals. by i ncorporating the vcm buffer into the adc , the ad7768 / ad7768 - 4 reduce component count and board space. in pin control mode , the vcm potentia l is fixed to ( avdd1 ? avss )/2 , and is enabled by default. in spi control mode, configure the vcm potential using the general configuration register (register 0x05 ) . the output can be enabled or disabled, and set to ( avdd1 ? avss )/2, 1.65 v, 2.14 v, or 2.5 v , with respect to avss . the vcm voltage output is associated with the channel 0 circuitry. if channel 0 is put into standby mode, the vcm voltage output is also disabled for maximum power savings. channel 0 must be enabled while vcm is being used externally to the ad7768 / ad7768 - 4 . reference input the ad7768 / ad7768 - 4 ha ve two differential reference input pairs . on the ad7768 ref1+ and ref1? are the reference inputs for channel 0 to channel 3, and ref2+ and ref2? are for channel 4 to channel 7. on the ad7768 - 4 ref1+ and ref1? are the reference inputs for channel 0 and channel 1, and ref2+ and ref2? are for chann el 2 and channel 3. the absolute input reference voltage range is 1 v to avdd 1 ? avss . like the analog inputs , the reference input s ha ve a precharge buffer option. each adc has an individual buffer for each ref x + and ref x? . the precharge buffers help redu ce the burden on the external reference circuitry . in pin control mode , the reference precharge buffers are o ff by default . i n spi control mode , the user can enable or disable the reference precharge buffers. i n the case of unipolar analog supplies , in spi control mode, the user can achieve the best performance and power efficiency by enabl ing only the ref x + buffers. the reference input current scale s linearly with the modulator clock rate. for 32 mhz mclk and mclk/ 4 fast mode, the differential input curren t is ~72 a / v per channel unbuffered , and ~ 16 a / v p er channel with the precharge buffers enabled. with the p recharge buffer s off , ref x + = 5 v, and ref x? = 0 v , ref x = 5 v 72 a / v = 360 a with the p recharge buffer s on , refx+ = 5 v, and refx? = 0 v , ref x = 5 v 16 a / v = 80 a for the best performance and headroom, it is recommended to use a 4.096 v reference such as the adr444 or the adr4540 . for the best performance at high sampling rates , it is recommended to use an external reference drive amplifier such as the ada4841 - 1 or the ad8031 . clock s election the ad7768 / ad7768 - 4 ha ve an internal oscillator that is used for initial power - up of the device. after the ad7768 / ad7768 - 4 have completed their start - up routine, the devices normally transfer control of the internal clocking to the externally applied mclk. the ad7768 / ad7768 - 4 count the falling edges of the external mclk over a given number of intern al clock cycles to determine if the clock is valid and at least a frequency of 1 .15 mhz . if there is a fault with the external mclk , the transfer of control does not occur , t he ad7768 / ad7768 - 4 output an error in the status header , and the clock error bit is set in the device status register. no conversio n data is output and a reset is required to exit this error state . three clock source input options are available to the ad7768 / ad7768 - 4 : e xternal cmos, c rystal o scillator , or lvds. the clock is select ed on power - up and is det ermined by the state of the clk_sel pin . if clk_sel = 0 , the cmos clock option is selected and the clock is applied to pin 32 (pin 31 is tied to dgnd). if clk_sel = 1 , the c rystal or lvds o ption is selected and the c rystal or lvds is applied to pin 31 and pin 32. the lvds opt ion is available only in spi control mode. an spi write to bit 3 of register 0x04 enables the lvds clock option. digital filtering the ad7768 / ad7768 - 4 offer two types of digital filters. in sp i control mode, these filters can be chosen on a per c hannel basis. in pin control mode, only one filter can be selected for all channels. the digital filters available on the ad7768 / ad7768 - 4 are ? sinc5 l ow latency filter, ? 3 d b at 0.2 04 odr ? wideband low ripple filter, ?3 db at 0.433 odr both filters can be operated in one of six different decimation rates, allowing the user to choose the optimal input bandwidth and speed of the conversion versus the desired power mode o r resolution.
data sheet ad7768 /ad7768 - 4 rev. a | page 57 of 99 sinc5 filter most precision - adcs use a sinc filter. the s inc5 filter offered i n the ad7768 / ad7768 - 4 enables a low latency signal path useful for dc inputs, for control loops, or where other specific post processing is required. th e sinc5 filter path offers the lowest noise and power consumption. the sinc 5 filter has a ? 3 db bw of 0.2 04 odr. table 13 contains the noise perform ance for the sinc5 filter across power modes and decimation ratios. 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 ?180 ?200 0 2 4 6 8 10 12 14 16 amplitude (db) normalized input frequenc y ( f in / f odr ) 14001-086 figure 87 . sinc5 f ilter f requency r esponse (decimation = 3 2) the settling times for the ad7768 / ad7768 - 4 when using the sin c 5 filter are shown in table 36. wideband low ripple filter the wideband filter has a low ripple pass band , within 0.005 db of ripple, of 0. 4 odr. the wideband filter has full attenuation at 0.499 odr (nyquist) , maximizing antialias protection. the wideband filter has a pass - band ripple of 0.00 5 d b and a stop band attenuation of 10 5 d b from nyquist out to f chop . for more information on an tialiasing and f chop aliasing , see the antialiasing section. the wideband filter is a very high order digital filter with a group delay of approximately 34/odr . after a synchronization pulse , there is an additiona l delay from the sync_in rising edge to fully settled data. the settling times for the ad7768 / ad7768 - 4 when using the wideband filter are shown in table 35. s ee table 12 for the noise performance of the wideband filter across power modes and decimation rates . 0 ?10 ?30 ?50 ?70 ?90 ?100 ?1 10 ?120 ?130 ?140 0 0.2 0.1 0.3 0.4 0.5 0.6 0.7 0.9 0.8 1.0 amplitude (db) normalized input frequenc y ( f in / f odr ) ?20 ?40 ?60 ?80 14001-088 figure 88 . wideband f ilter f requency response amplitude (db) ?0.010 0.010 0.008 ?0.008 0.006 ?0.006 0.004 ?0.004 0.002 ?0.002 0 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 normalized input frequenc y ( f in / f odr ) 14001-089 figure 89 . wideband f ilter p ass - b and r i pple 1.2 1.0 0.8 0.6 0.4 0.2 0 ?0.2 0 10 20 30 40 50 60 70 80 amplitude (db) output d at a r a te samples 14001-090 figure 90 . wideband f ilter s tep r esponse
ad7768/ad7768 - 4 data sheet rev. a | page 58 of 99 decimation rate cont rol the ad7768 / ad7768 - 4 ha ve programmable decimation rates for the digital filter s . the decimation rates allow the user to reduce the measure ment ba ndwidth, reduc ing the speed but increas ing the resolution . when using the spi control, c ontrol the decimation rate on the ad7768 / ad7768 - 4 through the c hannel m ode r egis - ters. these registers set two separate channel modes with a given decimation r ate and filter type. each adc is mapped to one of these m odes via the c hannel m ode s elect register. table 28 detail s both the decimation rates avail able , and the filter types for selection , within mode a and mode b. in pin control mode , the decimation ratio is controlled by the dec0 and dec1 pins ; see table 17 for decimation configuration in pin control mode. table 28 . channel x mode register s, regi ster 0x01 and register 0x02 bit s name logic value decimation r ate 3 filter_type_x 0 wideband filter 1 sinc5 filter [2:0] dec _ rate _x 000 32 001 64 010 128 011 256 100 512 101 1024 110 1024 111 1024 antialiasing because the ad7768 / ad7768 - 4 are switched capacitor, discrete time adcs, the user may wish to employ external analog antialias - ing filters to protect against fold back of out of band tones. within this section , an out of band tone refers to an input fre - quency greater than the pass band frequency specification of the digital filter that is applied at the analog input. when designing an antialiasing filter for the ad7768 / ad7768 - 4 , three main ali asing regions must be taken into account. after the alias requirements of each zone are understood, the user can design an antialiasing filter to meet the needs of the specific application. the three zones for consideration are related to the modulator sam pling frequency, the modulator chopping fre - quency, and the modulat or saturation point. modulator sampling frequency the ad7768 / ad7768 - 4 modulator signal transfer function includes a notch, at odd multiples of f mod , to reject tones or harmon ics related to the modulator clock . t he modulator itself attenuate signals at frequencies of f mod , 3 f mod ., 5 f mod , and so on. for an mclk frequency of 32.768 mhz, the attenuation is approx imately 35 db in fast mode, 41 db in median mode , a nd 53 db in e co m ode. attenuation is increased by 6 db across each power mode, with every halving of the mclk frequency , for example , when reducing the clock from 32.768 mhz to 16.384 mhz. the modulator has no rejection to signals that are at frequencies in zones arou nd 2 f mod and all even multiples of f mod. . signals at these frequencies are aliased by the ad7768 / ad7768 - 4 . for the ad7768 / ad7768 - 4 , the first of these zone s that requires protec - tion is at 2 f mod . because typical switch capacitor , discrete time - modulators provide no protection to alias ing at the frequency , f mod , the ad7768 / ad7768 - 4 provide a distinct advantage in this regard. figure 91 shows the frequency response of the modulator and wideband digital filter to out of band tones at the analog input. figure 91 shows the magnitude of an alias that is seen in band vs . the frequency of the sign al sampled at the analog input. the relationship between the input signal and the modulator frequency is expressed in a norm alized manner as a ratio of the input signal ( f in ) to the modulator frequency ( f mod ). this data demonstrates the adc frequency response relative to out of band tones when using the wideband filter. the input frequency (f in ) is swept from dc to 20 mhz . in f ast mode, u sing an 8.192mhz f mod frequency , the x - axis spans ratios of f in /f mod from 0 to 2.44 (equivalent to f in of 0 hz to 20 mhz) . a similar characteristic occurs in median and eco modes. the notch appears in fi gure 91 with the input frequency (f in ) at f mod ( designated at f in /f mod = 1.00 on the x - axis ) . an input at this frequency is attenuated by 35 db, which adds to the attenuation of any external anti alias ing filter , thus reducing the frequency roll - off requir ement of the external filter . if the plot is swept further in frequency , the notch is seen to recur at f in /f mod = 3.00 . the point where f in = 2 f mod (designated on the x - axis at 2.00) offers 0 db attenuation , indicating that all signals falling at this frequency alias directly back into the adc conversion results , in accordance with sampling theory. the ad7768 / ad7768 - 4 w ideband digital filter also offers an added protection against ali as ing . because the wideband filter has full attenuation at the nyquist frequency ( f odr /2 , where f odr = f mod /decimation rate ) , input frequencies , and in particular harmonics of input frequencies , that may fall close to f odr /2 , do not fold back into the pass - band of the ad7768 / ad7768 - 4 .
data sheet ad7768 /ad7768 - 4 rev. a | page 59 of 99 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 0.125 0.250 0.375 0.500 0.625 0.750 0.875 1.000 1.125 1.250 1.375 1.500 1.625 1.750 1.875 2.000 2.125 2.250 2.375 2.500 alias magnitude (db) with respect to in-band magnitude f chop = f mod /32 f chop = f mod /8 f in / f mod 14001-197 figure 91 . ad7768 / ad7768 - 4 rejection of out of band input tones, wideband filter, dec imation = 32, f mod = 8.192 mhz , analog input sweep from dc to 20 mhz modulator chopping frequency figure 91 plots two scenarios that relate to the chopping frequency of the ad7768 / ad7768 - 4 modulator s . the ad7768 / ad7768 - 4 use a chopping technique in the modula - tor similar to that of a chopped amplifier to remove offset, offset drift, and 1/f noise. the ad7768 / ad7768 - 4 default chopping rate is f mod /32. in pin control m ode, the chop frequency is hard wired to f mod /32. in spi control mode, the user can select the chop frequency to be either f mod /32 or f mod /8. as shown in figure 91 , the stop band rejection o f the digital filter is r educed at frequencies that relate to even multiples of the chopping frequency (f chop ). all other out of band frequencies (excluding those already discussed relating to the modulator clock frequency f mod ) are rejected by the stop band attenuation of the dig ital filter. an out of band tone with a frequency in the range of ( 2 f chop ) f 3db , where f 3db is the filter bandwidth employed, is attenuated to the envelope determined by the chop frequency setting (see figure 91 ) , and alias ed into the pass band . out of band tones near additional even multiples of f chop (that is, n f chop , where n is an even integer), are attenuated and aliased in the same way. chopping at f mod /32 offers the bes t performance for noise, offset, and offset drift for the ad7768 / ad7768 - 4 . for ac performance it may be useful to select c hopping at f mod /8 as this moves the first chopping tone to a higher frequency . however, chopping at f mod /8 may lead to slightly degraded noise (approximatel y 1 db loss in dynamic range) and offset performance compared to the default chop rate of f mod /32. table 29 shows the aliasing achieved by different order antialias ing filter options at the critical frequencies of f mod /32 and f mod /8 for chop aliasing , f mod /16 for modulator saturation , and 2 f mod for the f irst zone with 0 db attenuation . it assumes the corner frequency of the antialias ing filter is at f mod / 64, which is just above the maximum input bandwidth that t he a d7768 / ad7768 - 4 digital filter can pass when using a decimate by 32 filter setting . table 29 . external antialiasing filter attenuation rc filter f mod /32 (db) f mod /16 (db) f mod /8 (db) 2 f mod (db) first order ? 6 ? 12 ? 18 ? 42 second order ? 12 ? 24 ? 36 ? 84 third order ? 18 ? 36 ? 54 ? 126 modulator saturation point a - modulator can be considered a standard control loop, employing negative feedback. the control loop works to ensure that the average processed erro r signal is very small over time. it uses an integrator to remember preceding errors and force the mean error to be zero. as the input signal rate of change increases with respect to the modulator clock, f mod , a larger voltage feedback e rror is processed. above a certain frequency, the error begins to saturate the modulator. for the ad7768 / ad7768 - 4 , the modulator may saturate for full - scale input fre quencies greater than f mod /16, depending on the rate of change of input signal, input signal amplitud e, and reference input level. a half power input tone at f mod /8 also causes the modulator to saturate. in applications where there may be high amplitude and frequency out of band tones, a first - order antialias - ing filter is required with a ? 3 db corner frequency set at f mod /16 to protect against modulator saturation . for example , if operating the ad7768 / ad7768 - 4 at full speed and using a decimation rate of 32 to achieve a n output data rate of 256 k sps, the modulator rate is equal to 8.192 mhz. in this instance , to protect against saturation , set the antialias ing filter ? 3 db corner frequency to 512 khz. calibration in spi control mode, the ad7768 / ad7768 - 4 offer users the abilit y to adjust o ffset, g ain , and p hase delay on a per channel basis. offset adjustment the c hx _ offset _ msb , c hx _ offset _ mid, and c hx _ offset _ lsb registers are 24- bit , signed twos complement r egister s for channel offset adjustment. if the channel gain setting is at its ideal nominal value of 0x555555, an lsb of offset register adjustment changes the digital output by ? 4/3 lsbs. f or example, changing the offset register from 0 to 100 change s the digital output by ? 133 lsbs. because offset calibration occurs before gain calibration, the ratio of 4/3 change s linearly with gain adjustment via the c hannel x gain r egisters ( see table 56 and table 57 for the ad7768 , or table 82 and table 83 for the ad7768 - 4 ). after a reset or power cycle, the offset register values revert to the default factory setting.
ad7768/ad7768 - 4 data sheet rev. a | page 60 of 99 gain adjustment each adc channel has an associated gain coefficient. the coefficient is stored in three single - byte registers split up as msb, mid, an d lsb. each of the gain registers are factory programmed. nominally, this gain is around the value 0x555555 (for an adc channel). the user may overwrite the gain register setting . h owever, after a r eset or power cycle, the g ain register values revert to th e hard coded programmed factory setting. calculate t he approximate result that is output using the following formula : 42 21 2 300 , 194 , 4 4 ( 2 3 ? ? ? ? ? ? ? ? ? = gain offset) v v data ref in here offset is the offset register setting. gain is the gain register setting. sync phase offset adjustment the ad7768 / ad7768 - 4 ha ve one synchronization signal for all channels. the s ync phase offset register allows the user to vary the phase delay on each of the channels relative to the synchroniza - tion edge received on the sync_in pin. b y default, all adc channels react simultaneously to the sync_in pulse. the sync phase registers can be programmed to equalize known external phase differences on adc input channels , relative to one another. the range of phase compensat ion is limited to a maximum of one conversion cycle , and the resolution of the correction depends on the decimation rate in use. table 30 displays the resolution and register bits used for phase offset for each decim ation ratio. table 30 . phase d elay r esolution decimation ratio resolution steps phase r egister b its 32 1/ f mod 32 [7:3] 64 1/ f mod 64 [7:2] 128 1/ f mod 128 [7:1] 256 1/ f mod 256 [7:0] 512 2/ f mod 256 [7:0] 1024 4/ f mod 256 [7: 0] adjusting the sync phase of channels can affect the time to the first drdy pulse after the sync pulse, as well as the time to bit 6 of the header status (filter not settled data bit) being cleared, that is, the time to settled data. i f all channels are using the sinc5 filter, the time to the first drdy pulse is not affected by the adjustment of the sync phase offset, assuming that at least one channel has zero sync phase offset adjustment. if all channels have a nonze ro sync phase offset setting, the time to the first drdy pulse is delayed according to the channel that has the least offset applied. channels with a sync offset adjustment setting that delays the internal sync signal , relative to other c hannels , may not output settled data until after the next drdy pulse. in other words, there may be a delay of one odr period between the settled data being output by the ad7768 / ad7768 - 4 for the channels with added phase delay . i f all channels are using the wideband filter , the time to the first drdy pulse and the time to settled data is delayed according to the channel with the maximum phase delay setting. in this case , the interface waits for the latest channel and outputs data for all channels when that channel is ready.
data sheet ad7768 /ad7768 - 4 rev. a | page 61 of 99 data interface setting the format o f data output the data interface format is determined by setting the formatx pins. the logic state of the formatx pins are read on power - up and determine h ow many data lines (doutx) the adc conversion s are output on. because the formatx pins are read on power - up of the ad7768 and the device remains in this output configuration, th is function must always be hardwired and cannot be altered dynamically . table 31, figure 92 , figure 93 , and figure 95 show the formatting configuration for th e digital output pins on the ad7768 . calculate t he m inimum required dclk rate for a given data interface configuration as follows : dclk (min imum ) = output data r ate channels per dout x 32 w here mclk dclk. for example , if mclk = 32.768 mhz, with two doutx lines , dclk ( minimum ) = 256 k sps 4 channels per doutx 32 = 32.768 mbps therefore , dclk = mclk /1 . alternatively , i f mclk = 32.768 mhz, with eight doutx lines , dclk ( minimum ) = 256 k sps 1 channel per doutx 32 = 8.192 mbps therefore , dclk = mclk/ 4 . higher dclk rates make it easier to receive the conversion data from the ad7768 / ad7768 - 4 with a lower number of doutx l ines; however, there is a trade - off against adc offset performance with higher dclk frequencies. for the best offset and offset drift performance, use the lowest dclk frequency possible. the user can choose to reduce the dclk frequency by an appropriate se lection of mclk frequency, dclk divider, and/or the number of doutx lines used. table 1 and table 2 give the offset and offset drift specifications for ranges of dclk frequ ency, and figure 49 shows the typical offset drift over a range of dclk frequencies. table 31 . formatx truth table for the ad7768 format1 format0 description 0 0 each adc channel o utputs on its own dedicated pin. dout0 to dout7 are in use. 0 1 the adcs share the dout 0 and dout1 pins: channel 0 to channel 3 output on dout0. channel 4 to channel 7 output on dout1. the adc channels share data pins in time division multiplexed (tdm) ou tput. dout0 and dout1 are in use. 1 x all channels output on the dout0 pin , in tdm output. only dout0 is in use. table 32 . format0 truth table for the ad7768-4 format0 description 0 each adc channel outputs on its own dedicated pin. dout0 to dout3 are in use. 1 all channels output on the dout0 pin, in tdm output. only dout0 is in use. dout7 dout1 dout0 dclk drd y form a t1 dais y -chaining is not possible in this form a t dgnd form a t0 each adc has a dedic a ted doutx pin 0 0 ad7768 ch 0 ch 1 ch 7 14001-092 figure 9 2 . ad7768 formatx = 00, eight data output pins dout1 dout0 dclk drd y form a t1 dais y -chaining is possible in this form a t dgnd form a t0 iovdd channel0 t o channel3 output on dout0 channel4 t o channel7 output on dout1 1 0 ad7768 14001-193 figure 93 . ad7768 formatx = 01, two data output pins
ad7768/ad7768-4 data sheet rev. a | page 62 of 99 dout0 dclk drdy daisy-chaining is not possible in this format dgnd format0 each adc has a dedicated doutx pin 0 ad7768-4 ch 0 dout1 ch 1 dout2 ch 2 dout3 ch 3 14001-092 figure 94. ad7768-4 format0 = 0, four data output pins dout0 dclk drdy format1 daisy-chaining is possible in this format format0 iovdd channel0 to channel7 output on dout0 1 1 ad7768 14001-194 figure 95. ad7768 formatx = 10 or 11, or ad7768-4 format0 = 1, one data output pin adc conversion output: header and data the ad7768 data is output on the dout0 to dout7 pins, depending on the formatx pins. the ad7768-4 data is output on the dout0 to dout3 pins, depending on the format0 pin. the actual structure of the data output for each adc result is shown in figure 96. each adc result comprises 32 bits. the first eight bits are the header status bits, which contain status information and the channel number. the names of each of the header status bits are shown in table 33, and their functions are explained in the subsequent sections. this header is followed by a 24-bit adc output in twos complement coding, msb first. adc data n n ? 1 24 bits 8 bits doutx drdy header n 14001-093 figure 96. adc output: 8-bit header, 24-bit adc conversion data table 33. header status bits bit bit name 7 chip_error 6 filter not settled 5 repeated data 4 filter type 3 filter saturated [2:0] channel id[2:0] chip error the chip error bit indicates that a serious error has occurred. if this bit is set, a reset is required to clear this bit. this bit indicates that the external clock is not detected, a memory map bit has unexpectedly changed state, or an internal crc error has been detected. in the case where an external clock is not detected, the conversion results are output as all zeros regardless of the analog input voltages applied to the adc channels. filter not settled after power-up, reset, or synchronization, the ad7768/ ad7768-4 clear the digital filters and begins conversion. due to the weighting of the digital filters, there is a delay from the first conversion to fully settled data. the settling times for the ad7768/ ad7768-4 when using the wideband and sinc5 filters are shown in table 35 and table 36, respectively. this bit is set if this settling delay has not yet elapsed. repeated data if different channels use different decimation rates, data outputs are repeated for the slower speed channels. in these cases, the header is output as normal with the repeated data bit set to 1, and the following repeated adc result is output as all zeros. this bit indicates that the conversion result of all zeros is not real; it indicates that there is a repeated data condition because two different decimation rates are selected. this condition can only occur during spi control of the ad7768/ ad7768-4.
data sheet ad7768 /ad7768 - 4 rev. a | page 63 of 99 filter type in pin control mode , all channels operate using one filter selectio n. the filter selected in pin control mode is determined by the logic level of the filter pin. in spi control mode , the digital filters can be selected on a per channel basis , using the mode registers. t h is h eader bit is 0 for channels using the w ideband f ilter, and 1 for channels using the s inc5 f ilter . filter saturated the filter saturated bit i ndicates that the filter output is clipping at either positive or negative f ull scale. the digital filter clip s if the signal goes beyond the specificatio n of the filter ; it does not wrap. the clipping may be caused by the analog input exceeding the analog input range, or by a step change in the input , which may cause overshoot in the digital filter. clipping may also occur when the combination of the analog input s ignal and the channel gain register setting cause the signal seen by the filter to be higher than the analog input range. channel id the channel id bits i ndicate the adc channel from which the succeeding conversion data originates ( see table 34) . table 34. channel id vs . channel number channel channel id 2 channel id 1 channel id 0 channel 0 0 0 0 channel 1 0 0 1 channel 2 0 1 0 channel 3 0 1 1 channel 4 1 0 0 channel 5 1 0 1 chan nel 6 1 1 0 channel 7 1 1 1 data interface: standard conversion operation in standard mode operation, the ad7768 / ad7768 - 4 operate as the master and stream data to the dsp or fpga . the ad7768 / ad7768 - 4 suppl y the data, the data clock (d clk), and a falling edge framing signal ( drdy ) to the slave device. all of these signals are synchronous. the data interface connection s to dsp/fpga are shown in figure 102. the formatx pins deter mine how the data is output from the ad7768 / ad7768 - 4 . figure 97 through figure 99 show the data interface operating in standard mode at the maximum data rate. i n all instances, drdy is asserted one clock cycle before the msb of the data conversion is made available on the data pin. each drdy falling edge starts the output of the new adc conversion data. the first eight bits outp ut after the drdy falling edg e are the header bits ; the last 24 bits are the adc conversion result . figure 97, figure 98 , and figure 99 are distinct examples of the impact of the formatx pins on the ad7768 output operating in sta ndard conversion operation. figure 100 and fig ure 101 show two examples of the ad7768 - 4 interface configuration. figure 97 to figure 99 represent r unning the ad7768 at maximum data rate for the three formatx options. figure 97 shows formatx = 00 each adc has its own data out pin running at the mclk/4 bit rate. in pin control mo de, this is achieved b y selecting mode 0xa (fast mode, dclk = mclk/4, standard conversion , see table 20 ) with the decimation rate set as 32. figure 98 shows formatx = 01 share dout1 at the maxi mum bit rate . in pin control mode, this is achieved by selecting mode 0x 8 (fast mode, dclk = mclk/1, standard conversion) with a decimation rate of 32. if running in pin control mode, the example shown i n figure 9 9 represents mode 0x 4 (median mode, dclk = mclk/1, standard conversion) with a decimation rate of 32, giving the maximum output data capacity possible on one doutx pin. dclk drdy sample n sample n + 1 d0 d31 d4 d5 d28 d30 d29 d27 d0 d1 d2 d3 dout0 d... d31 d4 d5 d28 d30 d29 d27 d0 d1 d2 d3 d... d... d... dout1 d0 d31 d4 d5 d28 d30 d29 d27 d0 d1 d2 d3 d31 d4 d5 d28 d30 d29 d27 d0 d1 d2 d3 d... d... dout7 d0 d31 d4 d5 d28 d30 d29 d27 d0 d1 d2 d3 d31 d4 d5 d28 d30 d29 d27 d0 d1 d2 d3 14001-095 figure 97 . ad7768 formatx = 00 : each adc h as a dedicated d ata o ut put p in, m aximum d ata r ate
ad7768/ad7768 - 4 data sheet rev. a | page 64 of 99 ch0 (n) ch1 (n) ch2 (n) ch3 (n) ch0 (n+1) ch1 (n+1) ch2 (n+1) ch3 (n+1) ch4 (n) ch5 (n) ch6 (n) ch7 (n) ch4 (n+1) ch5 (n+1) ch6 (n+1) ch7 (n+1) dclk drd y dout0 sample n sample n + 1 dout1 dout7 dout2 14001-096 figure 98 . ad7768 format x = 01 : channel 0 to channel 3 s hare dout0, and channel 4 to channel 7 s hare dout1, m aximum d ata r ate dclk drdy dout0 sample n sample n + 1 sample n + 2 dout7 dout1 14001-097 figure 99 . ad7768 format x = 11 or 10 : channel 0 to channel 7 o utput on dout0 o nly, m aximum d ata r ate dclk drdy sample n sample n + 1 d0 d31 d4 d5 d28 d30 d29 d27 d0 d1 d2 d3 dout0 d... d31 d4 d5 d28 d30 d29 d27 d0 d1 d2 d3 d... d... d... dout1 d0 d31 d4 d5 d28 d30 d29 d27 d0 d1 d2 d3 d31 d4 d5 d28 d30 d29 d27 d0 d1 d2 d3 d... d... dout2 d0 d31 d4 d5 d28 d30 d29 d27 d0 d1 d2 d3 d31 d4 d5 d28 d30 d29 d27 d0 d1 d2 d3 d... d... dout3 d0 d31 d4 d5 d28 d30 d29 d27 d0 d1 d2 d3 d31 d4 d5 d28 d30 d29 d27 d0 d1 d2 d3 14001-395 figure 100 . ad7768 - 4 format0 = 0: each adc has a dedicated data output pin, maximum data rate
data sheet ad7768 /ad7768 - 4 rev. a | page 65 of 99 dclk drdy dout0 sample n sample n + 1 sample n + 2 dout1 dout2 dout3 14001-302 figure 101 . ad7768 - 4 format0 = 1: channel 0 to channel 3 output on dout0 only, maximum data rate dsp/fpg a ad7768 dclk drd y dout0 t o dout7 mclk 14001-094 figure 102 . data interface: standard conversion operation, ad7768 = master, dsp/fpga = slave sync_in dout0 dout1 drd y 32 dclks 32 dclks dout7 t settle settled dat a settled dat a settled dat a settled dat a settled dat a settled dat a 14001-098 figure 103 . ad7768 one - shot mode
ad7768/ad7768 - 4 data sheet rev. a | page 66 of 99 data int erface: one - shot conversion operation one - shot mode is available in both spi and pin control modes. this conversion mode is available by sele cting one of mode 0xc to mode 0xf when in pin control mode . in spi c ontrol mode, set bit 4 ( one s hot ) of register 0 x06 , the data control register. figure 103 shows the device operating in one - shot mode. in o ne - s hot mode , the ad7768 / ad7768 - 4 are pseud o slave s . conversions occur on request by the master device, for example, the dsp or fpga. t he sync_in pin initiat es the conversion request . in one - shot mode, all adcs run continuously ; however, the rising edge of the sync_ in pin controls the point in time from which data is output. to receive data , the master must pulse the sync_in pin t o re set the filter and force drdy low. drdy subsequently go es high to indicate to the master device that the device has valid settled data available. unlike standard mode , drdy remains high for the num ber of clock periods of valid data before it goes low again ; th us , in this conversion mode , it is an active high frame of the data. when the master pulses sync_in and the ad7768 / ad7768 - 4 receive the rising edge of this signal, the digital filter is reset and the full settling time of the filter elapses before the data is available. the duration of the settling time depends on the filter path and decimation rate. running one - shot mode with the sinc5 filter allows the fastest throughput, because this filter has a lower settling time than the wideband filter. as soon as settled data is available o n any channel , the device outputs data from all channels . t he contents of b it 6 of the channel header status bits indicate s whether the data is fully settled. t he period before the data is settled on all channels (t settle ) i s shown i n figure 103. after the data has settled on all channels , drdy is asserted high and the device outputs the required settled data on all channels before drdy is asserted low. if the user config - ures th e same filter and decimation rate on each adc , the data is settled for all channels on the first drdy output frame , which avoids a period of unsettled data prior to the settled data and ensures that all data is output at the same time on all adcs. the device then waits for another sync_in signal before outputting more data. because all the adcs are sampling continuously, o ne - s hot m ode affect s the sampling theory of the ad7768 / ad7768 - 4 . particularly , a user period ically send ing a sync_in pulse to the device is a form of sub sampling of the adc output. the subsampling occurs at the rate of the sync_in pulses. the sync_in pulse must be synchronous with the master c lock to ensure coherent sampling and to reduce the effects of jitter on the frequency response. daisy - chaining daisy - chaining devices allows numerous devices to use the same data interface lines by cascading the outputs of multiple adcs from separate ad7768 / ad7768 - 4 devices. o nly one adc device has its data interface in direct connection with the digital host. for the ad7768 / ad7768 - 4 , this connection can be implemented by cascading dout0 and dout1 through a number of devices, or just usi ng dout0 ; w hether two data output pins or only one data output pin is enabled depends on the f ormatx pins. the ability to daisy - chain devices and the limit on the number of devices that can be handled by the chain is dependen t on the p ower m ode, dclk , and the d ecimation r ate employed. the maximum usable dclk frequency allo wed when daisy - chaining devices is limited by the combin ation of timing specifications i n table 3 or tab le 5 , as well as by the propagation de lay of the data between devices and any skew between the mcl k signals at each ad7768 / ad7768 - 4 device. the propagation delay and mclk skew are dependent on the pcb layout and trace lengths. this feature is es pecially useful for reducing component count and wiring connections, for example, in isola ted multi converter applications or for systems with a limited interfacing capacity. when daisy - chaining, on the ad7768 , dout6 and dout7 become serial data inputs , and dout0 and dout1 remain as serial data outputs under the cont rol of the formatx pins. for the ad7768 - 4 the din pin is the daisy chain serial data input pin and dout0 is the serial data output pin. start sync_in dout1 dout0 drdy dout6 mclk dout7 sync_out dsp/ fpga start sync_in dout1 dout0 drdy dout6 mclk dout7 sync_out dnc dnc iovdd iovdd start sync_in dout1 dout0 drdy dout6 mclk dout7 sync_out dnc dnc ad7768 ad7768 ad7768 synchronization logic digital filter synchronization logic digital filter synchronization logic digital filter master clock 14001-099 figure 104 . daisy - chai ning multiple ad7768 devices figure 104 shows an example of daisy - chaining ad7768 devices, when formatx = 01. in this case, the dout1 and dout0 pins of the ad7768 devices are cascaded to the dout6 and dout7 pins of the next device in the chain. data readbac k is
data sheet ad7768/ad7768 -4 rev. a | page 67 of 99 analogous to clocking a shift register where data is clocked on the rising edge of dclk. the scheme operates by passing the output data of the dout0 and dout1 pins of an ad7768 upstream device to the dout6 and dout7 inputs of the next ad776 8 device downstream in the chain. the data then continues through the chain until it is clocked onto the dout0 and dout1 pins of the final d own - stream device in the chain. the devices in the chain must be synchronized by using one of the following methods: ? applying a synchronous signal to the sync_in pin of all devices in the chain ? by routing the sync_out pin of the first device to the sync_in pin of that same device and to the sy nc_in pins of all other devices in the chain and applying an asynchronous signal to the start input. ? issuing an spi_sync command over the spi control interface. figure 104 shows the configurat ion where an asynchronous signal is applied to the start pin , and the sync_out pin of the first device is connected to the sync_in pins of all devices in the chain daisy chaining can be achieved in a si milar manner on the ad7768 and ad7768 -4 when using only the dout0 pin. in this case , only pin 21 of the ad7768 / ad7768 -4 is us ed as the serial data input pin. in a daisy - chained system of ad7768 / ad7768 -4 devices , two successive synchronization pulses must be applied to guarantee that all adcs are synchronized. two synchronization pulses are also required in a system of more than one ad7768 / ad7768 -4 devic e sharing a single mclk signal, where the drdy pin of only one device is used to detect new data. the maximum dclk frequency that can be used when daisy - chaining devices is a function of the ad7768 / ad7768 -4 timing specifications (t 4 , t 8 , and t 11 i n table 3 and table 5 ) and any timing differences between the ad7768 / ad7768 -4 devices due to layout and spacing of devices on the pcb. use t he fo llowing formula to aid in determining the maximum operating frequency of the interface: ) (2 1 skew p 8 4 11 max ttttt f ++++ = f max is the maximum useable dclk frequency. t 11 , t 4 , and t 8 are the ad7768 / ad7768 -4 timing specifications (see table 3 and table 5 ). t p is the maximum propagation delay of the data between successive ad7768 / ad7768 -4 devices in the chain. t skew is the maximum skew in the mclk signal seen by a ny pair of ad7768 / ad7768 -4 devices in the chain. synchronization an important consideration for daisy - chaining more than two ad7768 / ad7768 -4 devices is synchronization. the basic provision for synchronizing multiple devices is that each d evice is clocked with the same base mclk signal. the ad7768 / ad7768 -4 offer three options to allow ease of system synchro nization. choosing between the options depends on the system , but is determined by whether the user can supply a synchronizati on pulse that is truly synchronous with the base mclk signal. if the user cannot provide a signal that is synchronous to the base mclk signal , one of the following two methods can be employed: ? apply a start pulse to the first ad7768 or ad7768 -4 device. the first ad7768 or ad7768 -4 device samples the asynchronous start pulse and generates a pulse on sync_out of the first device related to the base mclk signal for distribution local ly. ? use s ynchronization over spi (o nly available in spi c ontrol m ode ) to w rite a synchronization command to the first ad7 768 or ad7768 -4 device. similarly to the start pin method , the spi sync generates a pulse on sync_out of the first device related to the base mclk signal for distribution local ly . in both cases, route the sync_out pin of the first device to the sync_in pin of that same device and to the sync_in pins of all other devices that are to be synchr onized (s ee figure 105 ). the sync_out pins of the other devices must remain open circuit. tie a ll unused start pins to a l ogic 1 through pull - up resistors. 14001-303 start sync_in dout1 dout0 drdy mclk sync_out dsp/ fpga ad7768/ ad7768-4 synchronization logic digital filter start sync_in drdy mclk sync_out ad7768/ ad7768-4 synchronization logic digital filter master clock dnc dnc iovdd figure 105 . synchronizing multiple ad7768 / ad7768 -4 devices using sync_out
ad7768/ad7768-4 data sheet rev. a | page 68 of 99 if the user can provide a signal that is synchronous to the base mclk, this signal can be applied directly to the sync_in pin. route the signal from a star point and connect it directly to the sync_in pin of each ad7768/ ad7768-4 device (see figure 106). the signal is sampled on the rising mclk edge; setup and hold times are associated with the sync_in input are relative to the ad7768/ ad7768-4 mclk rising edge. in this case, tie the start pin to logic 1 through a pull-up resistor; sync_out is not used and can remain open circuit. 14001-304 sync_in dout1 dout0 drdy mclk dsp/ fpga ad7768/ ad7768-4 synchronization logic digital filter dout1 dout0 drdy sync_in mclk ad7768/ ad7768-4 synchronization logic digital filter start iovdd start iovdd figure 106. synchronizing multiple ad7768 / ad7768-4 devices using only sync_in crc check on data interface the ad7768/ ad7768-4 deliver 32 bits per channel as standard, which by default consists of 8 status header bits and 24 bits of data. the header bits default per the description in table 33. however, there is also the option to employ a crc check on the adc conversion data. this functionality is available only when operating in spi control mode. the function is controlled by crc_select in the interface configuration register (register 0x07). when employed, the crc message is calculated internally by the ad7768/ ad7768-4 on a per channel basis. the crc then replaces the 8-bit header every four samples or every 16 samples. the following is an example of how the crc works for four- sample mode (see figure 107): 1. after a synchronization pulse is applied to the ad7768/ ad7768-4 , the crc register is cleared to 0xff. 2. the next four 24-bit conversion data samples (n to n + 3) for a given channel stream into the crc calculation. 3. for the first three samples that are output after the synchronization pulse (n to n + 2), the header contains the normal status bits. 4. for the fourth sample after the synchronization pulse (n + 3), the 8-bit crc is sent out instead of the normal header status bits, followed by the sample conversion data. this crc calculation includes the conversion data that is output immediately after the crc header. 5. the crc register is then cleared back to 0xff and the cycle begins again for the fifth to eighth samples after the synchronization pulse. it is possible to have channels outputting at different rates (for example decimation by 32 on channel 0 and decimation by 64 on channel 1). in such cases, the crc header still appears across all channels at the same time, that is, at every fourth drdy pulse after a synchronization. for the channels operating at a relatively slower odr, the crc is still calculated and emitted every 4 or 16 drdy cycles, even if this means that the nulled data is included. therefore, a crc is calculated for only nulled samples or for a combination of nulled samples and actual conversion data. the ad7768/ ad7768-4 use a crc polynomial to calculate the crc message. the 8-bit crc polynomial used is x 8 + x 2 + x + 1. to generate the checksum, the data is left shifted by eight bits to create a number ending in eight 1s. the polynomial is aligned such that its msb is adjacent to the leftmost logic 1 of the data. an exclusive or (xor) function is applied to the data to produce a new, shorter number. the polyno- mial is again aligned such that its msb is adjacent to the leftmost logic 1 of the new result, and the procedure is repeated. this process repeats until the original data is reduced to a value less than the polynomial. this is the 8-bit checksum. n ? 1 dout0 drdy header n 8 bits data n header n + 1 data n + 1 header n + 2 data n + 2 crc data n + 3 24 bits 8 bits 24 bits 8 bits 24 bits 8 bits 24 bits 14001-100 figure 107. crc 4-bit stream
data sheet ad7768/ad7768 - 4 rev. a | page 69 of 99 table 35 . wideband filter sync_in to s ettled data power mode filter type decimation factor delay from first mclk rise after sync_in rise to first drdy rise delay from first mclk rise after sync_in rise to earliest settled data drdy rise mclk periods group a group b group a group b mclk periods group a group b fast wideband wideband 32 unu sed 336 8400 n ot applicable wideband wideband 64 unused 620 16,748 not applicable wideband wideband 128 unused 1187 33,443 not applicable wideband wideband 256 unused 2325 66,837 not applicable wideband wideband 512 unused 4601 133,625 not applicab le wideband wideband 1024 unused 9153 267,201 not applicable wideband wideband 32 32 758 8822 8822 wideband wideband 32 64 758 8822 17,014 wideband wideband 32 128 758 8822 33,526 wideband wideband 32 256 758 8822 66,934 wideband wideband 32 512 758 8822 133,622 wideband wideband 32 1024 758 8822 267,253 wideband wideband 64 32 759 17,015 8823 wideband wideband 128 32 760 33,528 8824 wideband wideband 256 32 762 66,938 8826 wideband wideband 512 32 782 133,646 8846 wideband wideband 1024 32 806 267,302 8870 median wideband wideband 32 unused 656 16,784 not applicable wideband wideband 64 unused 1225 33,481 not applicable wideband wideband 128 unused 2359 66,871 not applicable wideband wideband 256 unused 4635 133,659 not applic able wideband wideband 512 unused 9187 267,235 not applicable wideband wideband 1024 unused 18,291 534,387 not applicable wideband wideband 32 32 820 16,948 16,948 wideband wideband 32 64 820 16,948 33,588 wideband wideband 32 128 820 16,948 66,8 68 wideband wideband 32 256 820 16,948 133,684 wideband wideband 32 512 820 16,948 267,316 wideband wideband 32 1024 820 16,948 534,580 wideband wideband 64 32 822 33,590 16,950 wideband wideband 128 32 824 66,872 16,952 wideband wideband 256 3 2 844 133,708 16,972 wideband wideband 512 32 836 267,332 16,964 wideband wideband 1024 32 852 534,612 16,980 eco wideband wideband 32 unused 2587 67,099 not applicable wideband wideband 64 unused 4855 133,879 not applicable wideband wideband 128 unused 9391 267,439 not applicable wideband wideband 256 unused 18,495 534,591 not applicable wideband wideband 512 unused 36,703 1,068,895 not applicable wideband wideband 1024 unused 73,119 2,137,503 not applicable wideband wideband 32 32 2587 67 ,099 67,099 wideband wideband 32 64 2587 67,099 134,683 wideband wideband 32 128 2587 67,099 267,803 wideband wideband 32 256 2587 67,099 535,067 wideband wideband 32 512 2587 67,099 1,069,595 wideband wideband 32 1024 2587 67,099 2,137,627 wid eband wideband 64 32 2587 134,683 67,099 wideband wideband 128 32 2587 267,803 67,099 wideband wideband 256 32 2587 535,067 67,099 wideband wideband 512 32 2587 1,069,595 67,099 wideband wideband 1024 32 2587 2,137,627 67,099
ad7768/ad7768 - 4 data sheet rev. a | page 70 of 99 table 36. sinc5 f ilter sync_in to s ettled d ata 1 power mode filter type decimation factor delay from first mclk rise after sync_in rise to first drdy rise delay from first mclk rise after sync_in rise to earliest settled data drdy rise group a group b group a group b group a group b mclk periods mclk periods mclk periods fast sinc5 sinc5 32 unused 199 839 not applicable sinc5 sinc5 64 unused 327 1607 not applicable sinc5 sinc5 128 unused 583 3143 not applicable sinc5 sinc5 256 unused 1095 6215 not applicable sinc5 sinc5 512 unused 2119 12359 not applicable sinc5 sinc5 1024 unused 4167 24,647 not applicable sinc5 sinc5 32 32 199 839 839 sinc5 s inc5 32 64 199 839 1607 sinc5 sinc5 32 128 199 839 3143 sinc5 sinc5 32 256 199 839 6215 sinc5 sinc5 32 512 199 839 12,359 sinc5 sinc5 32 1024 199 839 24,647 sinc5 sinc5 64 32 199 1607 839 sinc5 sinc5 1024 32 199 24,647 839 median sinc5 sinc5 3 2 unused 383 1663 not applicable sinc5 sinc5 64 unused 639 3199 not applicable sinc5 sinc5 128 unused 1151 6271 not applicable sinc5 sinc5 256 unused 2175 12,415 not applicable sinc5 sinc5 512 unused 4223 24,703 not applicable sinc5 sinc5 1024 un used 8319 49,279 not applicable sinc5 sinc5 32 32 383 1663 1663 sinc5 sinc5 32 64 383 1663 3199 sinc5 sinc5 32 128 383 1663 6271 sinc5 sinc5 32 256 398 1663 12,415 sinc5 sinc5 32 512 398 1663 24,703 sinc5 sinc5 32 1024 398 1663 49,279 sinc5 s inc5 64 32 383 3199 1663 sinc5 sinc5 1024 32 398 49,279 1663 eco sinc5 sinc5 32 unused 1487 6607 not applicable sinc5 sinc5 64 unused 2511 12,751 not applicable sinc5 sinc5 128 unused 4559 25,039 not applicable sinc5 sinc5 256 unused 8655 49,615 n ot applicable sinc5 sinc5 512 unused 16,847 98,767 not applicable sinc5 sinc5 1024 unused 33,231 197,071 not applicable sinc5 sinc5 32 32 1487 6607 6607 sinc5 sinc5 32 64 1487 6607 12,751 sinc5 sinc5 32 128 1487 6607 25,039 sinc5 sinc5 32 256 1 487 6607 49,615 sinc5 sinc5 32 512 1487 6607 98,767 sinc5 sinc5 32 1024 1487 6607 197,071 sinc5 sinc5 64 32 1487 12,751 6607 sinc5 sinc5 1024 32 1487 197,071 6607 1 this table is based on default internal clock divide setti ngs of mclk/4 in fast mode, mclk/8 in median mode, a nd mclk/32 in eco mode.
data sheet ad7768/ad7768 - 4 rev. a | page 71 of 99 functionality gpio functionality the ad7768 / ad7768 - 4 have additional gpio functionality when operated in spi mode. this fully configurable mode allows the device to operate five gpios. the gpiox pins can be set as inputs or outputs (read or write) on a per pin basis. in write mode, these gpio pins can be used to control ot her circuits such as switches, multiplexers, buffers, over the same spi interface as the ad7768 / ad7768 - 4 . sharing the spi interface in this way allows the user to use a lower overall number of data lines from the controller compared to a system wh ere multiple control signals are required. this sharing is especially useful in systems where reducing the number of control lines across an isolation barrier is important. see figure 108 and figure 109 for details of the gpio pin options available on the ad7768 and ad7768 - 4 , respectively. similarly, a gpio read is a useful feature because it allows a peripheral device to send information to the input gpio and then this information can be read from the spi interface of the ad776 8 / ad7768 - 4 . 12 13 14 15 t o dsp/fpg a 1 1 17 st1/sclk 18 dec1/sdi 19 dec0/sdo 20 dout7 21 dout6 22 dout5 23 dout4 24 dout3 25 dout2 14001-101 mode0/gpio0 mode1/gpio1 mode2/gpio2 mode3/gpio3 fi l ter/gpio4 gpio pins 16 st0/cs figure 108 . ad7768 gpio functionality 12 13 15 to dsp/fpga 11 17 sclk 18 dec1/sdi 19 dec0/sdo 20 dnc/dgnd 21 din 22 dnc 23 dnc 24 dout3 25 dout2 14001-305 mode0/gpio0 mode1/gpio1 mode3/gpio3 filter/gpio4 gpio pins 14 mode2/gpio2 16 st0/cs figure 109 . ad7768 - 4 gpio functionality configuration control and read back of the gpiox pins are set in register 0x0e, register 0x0f, and register 0x10 (see table 49 , table 50 , and table 51 for more i nformation for the ad7768 , a nd table 75, table 76 , and table 77 for the ad7768 - 4 ).
ad7768/ad7768 - 4 data sheet rev. a | page 72 of 99 ad7768 register map details (spi control) ad7768 register map see table 63 and the ad7768 - 4 register map details (spi control) section for the ad7768 - 4 register map and register functions. table 37 . detailed ad7768 register map reg. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x00 channel s tandby ch_7 ch_6 ch_5 ch_4 ch_3 ch_2 ch_1 ch_0 0x00 rw 0x01 channel mode a unused filter_type_a dec_rate_a 0x0d rw 0x02 channel mode b unused filter_type_b dec_rate_b 0x0d rw 0x03 channel m ode s elect ch_7_mode ch_6_mode ch_5_mode ch_4_mode ch_3_mode ch_2_mode ch_1_mode ch_0_mode 0x00 rw 0x04 power_mode slee p_mode unused power_mode lvds_enable unused mclk_div 0x00 rw 0x05 general c onfiguration unused reserved retime_en vcm_pd reserved unused vcm_vsel 0x08 rw 0x06 data c ontrol spi_sync unused single_shot_en unused spi_reset 0x80 rw 0x07 interface c onfigura tion unused crc_select dclk_div 0x0 rw 0x08 bist c ontrol unused ram_bist_ start 0x0 rw 0x09 device s tatus unused chip_error no_clock_ error ram_bist_pass ram_bist_ running 0x0 r 0x0a revision id revision_id 0x06 r 0x0b reserved reserved 0x00 r 0x0c re served reserved 0x00 r 0x0d reserved reserved 0x00 r 0x0e gpio c ontrol ugpio_ enable unused gpioe4_filter gpioe3_mode3 gpioe2_mode2 gpioe1_mode1 gpio0_mode0 0x00 rw 0x0f gpio write data unused gpio4_write gpio3_write gpio2_write gpio1_write gpio0_write 0x00 rw 0x10 gpio read data unused gpio4_read gpio3_read gpio2_read gpio1_read gpio0_read 0x00 r 0x11 precharge buffer 1 ch3_prebuf_ neg_en ch3_prebuf_ pos_en ch2_prebuf_ n eg_en ch2_prebuf_ pos_en ch1_prebuf_ neg_en ch1_prebuf_ pos_en ch0_prebuf_ neg_en c h0_prebuf_ pos_en 0xff rw 0x12 precharge buffer 2 ch7_prebuf_ neg_en ch7_prebuf_ pos_en ch6_prebuf_ n eg_en ch6_prebuf_ pos_en ch5_prebuf_ neg_en ch5_prebuf_ pos_en ch4_prebuf_ neg_en ch4_prebuf_ pos_en 0xff rw 0x13 positive reference precharge buffer ch7_r efp_ buf ch6_refp_ buf ch5_refp_ buf ch4_refp_buf ch3_refp_buf ch2_refp_buf ch1_refp_buf ch0_refp_ buf 0x00 rw 0x14 negative reference precharge buff er ch7_refn_ buf ch6_refn_ buf ch5_refn_ buf ch4_refn_buf ch3_refn_buf ch2_refn_buf ch1_refn_buf ch0_refn_ buf 0x00 rw 0x1e channel 0 o ffset ch0_offset_msb 0x00 rw 0x1f ch0_offset_mid 0x20 ch0_offset_lsb 0x21 channel 1 o ffset ch1_offset_msb 0x00 rw 0x22 ch1_offset_mid 0x23 ch1_offset_lsb 0x24 channel 2 o ffset ch2_offset_msb 0x00 rw 0x25 c h2_offset_mid 0x26 ch2_offset_lsb 0x27 channel 3 o ffset ch3_offset_msb 0x00 rw 0x28 ch3_offset_mid 0x29 ch3_offset_lsb 0x2a channel 4 o ffset ch4_offset_msb 0x00 rw 0x2b ch4_offset_mid 0x2c ch4_offset_lsb 0x2d channel 5 o ffset ch5_o ffset_msb 0x00 rw 0x2e ch5_offset_mid 0x2f ch5_offset_lsb 0x30 channel 6 o ffset ch6_offset_msb 0x00 rw 0x31 ch6_offset_mid 0x32 ch6_offset_lsb 0x33 channel 7 o ffset ch7_offset_msb 0x00 rw 0x34 ch7_offset_mid 0x35 ch7_offset_lsb
data sheet ad7768/ad7768 - 4 rev. a | page 73 of 99 reg. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0 x36 channel 0 g ain ch0_gain_msb 0xxx rw 0x37 ch0_gain_mid 0x38 ch0_gain_lsb 0x39 channel 1 g ain ch1_gain_msb 0xxx rw 0x3a ch1_gain_mid 0x3b ch1_gain_lsb 0x3c channel 2 g ain ch2_gain_msb 0xxx rw 0x3d ch2_gain_mid 0x3e ch2_gain_lsb 0x3f channel 3 g ain ch3_gain_msb 0xxx rw 0x40 ch3_gain_mid 0x41 ch3_gain_lsb 0x42 channel 4 g ain ch4_gain_msb 0xxx rw 0x43 ch4_gain_mid 0x44 ch4_gain_lsb 0x45 channel 5 g ain ch5_gain_msb 0xxx rw 0x46 ch5_gain_mid 0x47 ch5_gain_lsb 0x48 channel 6 g ain ch6_gain_msb 0xxx rw 0x49 ch6_gain_mid 0x4a ch6_gain_lsb 0x4b channel 7 g ain ch7_gain_msb 0xxx rw 0x4c ch7_gain_mid 0x4d ch7_gain_lsb 0x4e channel 0 sync offset ch0_sync_offset 0x00 rw 0x4f channel 1 sync offset ch 1_sync_offset 0x00 rw 0x50 channel 2 sync offset ch2_sync_offset 0x00 rw 0x51 channel 3 sync offset ch3_sync_offset 0x00 rw 0x52 channel 4 sync offset ch4_sync_offset 0x00 rw 0x53 channel 5 sync offset ch5_sync_offset 0x00 rw 0x54 channel 6 sync offse t ch6_sync_offset 0x00 rw 0x55 channel 7 sync offset ch7_sync_offset 0x00 rw 0x56 diagnostic receiver ( rx ) ch7_rx ch6_rx ch5_rx ch4_rx ch3_rx ch2_rx ch1_rx ch0_rx 0x00 rw 0x57 diagnostic mux control unused grpb_sel unused grpa_sel 0x00 rw 0x58 modulato r delay control unused clk_mod_del_en reserved 0x02 rw 0x59 chop c ontrol unused grpa_chop grpb_chop 0x0a rw
ad7768/ad7768 - 4 data sheet rev. a | page 74 of 99 channel standby regi ster address: 0x00, reset: 0x00, name: channel standby each of the adc channels can be put into standby mode independently by setting the appropriate bit in the c hannel s tandby register. when a channel is in standby mode , its position in the data output stream is held. the 8 - bit header is all zero s , as is the conversion result output of 24 zeros. the vcm voltage output is associ ated with the channel 0 circuitry. if channel 0 is put into standby mode, the vcm voltage output is also disabled for maximum power savings. channel 0 must be enabled while vcm is being used externally to the ad7768 . the crystal excitation circuitry is associated with the channel 4 circuitry. if channel 4 is put int o standby mode, the crystal circuitry is also disabled for maximum power savings. channel 4 must be enabled while the external crystal is used on the ad7768 . table 38 . bit descriptions for channel standby bits bit name settings description reset access 7 ch_7 channel 7 0x0 rw 0 enabled 1 standby 6 ch_6 channel 6 0x0 rw 0 enabled 1 standby 5 ch_5 channel 5 0x0 rw 0 enabled 1 standby 4 ch_4 channel 4 0x0 rw 0 enabled 1 standby 3 ch_3 channel 3 0x0 rw 0 enabled 1 standby 2 ch_2 channel 2 0x0 rw 0 enabled 1 standby 1 ch_1 channel 1 0x0 rw 0 enabled 1 standby 0 ch_0 channel 0 0x0 rw 0 enabled 1 standby channel mode a regis ter address: 0x01, reset: 0x 0d , name: channel mode a two m ode options are available on the ad7768 adcs. the c hannel m odes are defined by the con tents of the channel mode a and channel mode b registers. each mode is then mapped as desired to the required adc channel. channel mode a and channel mode b allow different filter types and decimation rates to be selected and mapped to any of the adc chann els. when different decimation rates are selected , the ad7768 output a data ready signal at the fastest selected d ecimation rate. any channel that runs at a lower output data rate is updated only at that slower rate. in between valid result data , the data for that channel is set to zero and the r epeated d ata bit is set in the header status bits to distinguish it from a real conversion result (see the adc conversion output: header and data section) .
data sheet ad7768/ad7768 - 4 rev. a | page 75 of 99 table 39 . bit descriptions for channel mode a bits bi t name settings description reset access 3 filter_type_a filter s election 0x1 rw 0 wideband filter 1 sinc5 filter [2:0] dec_rate_a decimation r ate s electio n 0x5 rw 000 32 001 64 010 128 011 256 100 512 101 10 24 110 1024 111 1024 channel mode b regis ter address: 0x02, reset: 0x 0d , name: channel mode b table 40 . bit descriptions for channel mode b bits bit name settings description reset access 3 filter_type_b filter selec tion 0x1 rw 0 wideband filter 1 sinc5 filter [2:0] dec_rate_b decimation rate selection 0x5 rw 000 32 001 64 010 128 011 256 100 512 101 1024 110 1024 111 1024 channel mode select register addre ss: 0x03, reset: 0x00, name: channel mode select this register s elects the mapping of each adc channel to either channel mode a or channel mode b. table 41 . bit descriptions for channel mode select bits bit name settings description reset access 7 ch_7_mode channel 7 0x0 rw 0 mode a 1 mode b 6 ch_6_mode channel 6 0x0 rw 0 mode a 1 mode b 5 ch_5_mode channel 5 0x0 rw 0 mode a 1 mode b 4 ch_4_mode channel 4 0x0 rw 0 mode a 1 mode b 3 ch_3_ mode channel 3 0x0 rw 0 mode a 1 mode b
ad7768/ad7768 - 4 data sheet rev. a | page 76 of 99 bits bit name settings description reset access 2 ch_2_mode channel 2 0x0 rw 0 mode a 1 mode b 1 ch_1_mode channel 1 0x0 rw 0 mode a 1 mode b 0 ch_0_mode channe l 0 0x0 rw 0 mode a 1 mode b power mode select re gister address: 0x04, reset: 0x00, name: p ower _m ode table 42 . bit descriptions for power_mode bits bit name settings description reset access 7 sleep_mode in sleep mode, many of the digital clocks are disabled and all of the adcs are disa bled. the analog ldos are not disabled. 0x0 rw the ad7768 spi is live and is available to the user. writing to this bit brings the ad7768 out of sleep mode again. 0 normal o peration . 1 sleep mode . [5:4] power_mode power mode. the power mode bits control the power mode setting for the bias currents used on all adcs on the ad7768 . the user can select the current consumption target to meet the application. the power mod es of fast, median, and eco give optimum performance when mapped to the correct mclk division setting. these power mode bits do not control the mclk division of the adcs. see the mclk_div bits for control of the division of the mclk input. 0x0 rw 00 eco mode . 10 median mode . 11 fast mode . 3 lvds_enable lvds clock. 0x0 rw 0 lvds input clock disabled. 1 lvds input clock enabled. [1:0] mclk_div mclk division . the mclk division bits control the divided ratio between the mclk applied at the input to the ad7768 and the clock used by each of the adc modulators. the appropriate division ratio depends on the fol lowing factors: power mode, decimation rate, and the base mclk available in the system. see the clocking, sampling tree, and power scaling section for more information on setting mclk_ div correctly. 0x0 rw 00 m clk/32: w ith a base mclk of 32.768 mhz , set to mclk/32 for eco mode. 10 mclk/8: w ith a base mclk of 32.768 mhz , set to mclk/8 for median mode. 11 mclk/4: w ith a base mclk of 32.768 mhz , set to mclk/4 for fast mode. general device confi guratio n register address: 0x05, reset: 0x0 8 , name: general config uration table 43 . bit descriptions for general config uration bits bit name settings description reset access 5 retime_en sync_out signal retime enable bit . 0x0 rw 0 disabled: n ormal timing of sync_out . 1 enabled: sync_out signal derived from alternate mclk edge.
data sheet ad7768/ad7768 - 4 rev. a | page 77 of 99 bits bit name settings description reset access 4 vcm_pd vcm buffer power - down. 0x0 rw 0 enabled: vcm buffer normal mode. 1 powered down: v cm buffer powered down. [1:0] vcm_vsel vcm voltage. these bits select the output voltage of the vcm pin. this voltage is derived from the avdd1 supply and can be output as half of that avdd1 voltage, or other fixed voltages, with respect to avss. the v cm voltage output is associated with the channel 0 circuitry. if channel 0 is put into standby mode, the vcm voltage output is also disabled for maximum power savings. channel 0 must be enabled while vcm is being used externally to the ad7768 . 0x0 rw 00 (avdd1 ? avss)/2 v. 01 1.65 v. 10 2.5 v. 11 2 .14 v. data control: soft r eset, sync, and sing le - shot control registe r address: 0x06, reset: 0x80, name: data control table 44 . bit descriptions for data control bits bit name settings description reset access 7 spi_sync softwa re synchronization of the ad7768 . this command has the same e ffect as sending a signal pulse to the start pin. to operate the spi_sync , the user must write to this bit two separate times. first , writ e a zero , putting spi_ sync low, and then write a 1 to set spi_ sync logic high again. the spi_sync co mmand is recog - nize d after the last rising edge of sclk in the spi instruction where the spi_sync bit is changed from low to high. the spi_sync command is then output synchro - nous to the ad7768 mclk on the sync_out pin. the user must connect the sync_out signal to the sync_in pin on the pcb. the sync_out pin can also be routed to the sync_in pins of other ad7768 devices , allowing larger channel count simultaneous sampling systems. as per any synchronizatio n pulse seen by the sync_in pin, the digital filters of the ad7768 are reset. the full settling time of the filters must elapse before data is output on the data interface. in a daisy - chained system of ad7768 devices, two successive synchronization pulses must be applied to guarantee that all adcs are synchronized. two synchronization pulses are also required in a system of more than one ad7768 device sharing a single mclk signal, where the drdy pin of only one device is used to det ect new data. 0x1 rw 0 change to spi_sync low. 1 change to spi_sync high. 4 single_shot_en one -s hot m ode. enables o ne - s hot m ode. in o ne -s hot mode , the ad7768 output a conversion result in response to a sync_in rising edge. 0x0 rw 0 disabled . 1 enabled . [1:0] spi_reset soft r eset . these bits allow a full device reset over the spi port. two successive commands must be received in the correct order to generate a reset : first, w rite 0x03 to the s oft r eset r egister , and then w rite 0x02 to the s oft reset register . this sequence cau ses the digital core to reset and all registers return to their default values. following a soft reset , if the spi master sends a command to the ad7768 , the devices respond on the next frame to that command with an output of 0x0e00. 0x0 rw 00 no effect . 01 no effect . 10 second r eset c ommand . 11 fi rst r eset c ommand .
ad7768/ad7768 - 4 data sheet rev. a | page 78 of 99 interface configurat ion register address: 0x07, reset: 0x0, name: interface config uration table 45 . bit descriptions for interface config uration bits bit name settings description reset access [3:2] crc_select crc s elect. these bits a llow the user to implement a crc on the data interface. when selected , the crc replaces the header every fourth or 16 th output sample depending on the crc option chosen. there are two options for the crc ; both use the same polynomi al: x 8 + x 2 + x + 1. the options offer the user the ability to reduce the duty cycle of the crc calculation by performing it less often: in the case of having it every 16 th sample or m ore often in the case of every four th conversion. the crc is calculated on a per channel basis and it includes conversion data only. 0x0 rw 00 no crc. status bits with every conversion. 01 replace the header with crc message every 4 samples . 10 replace the header with crc message every 16 samples . 11 replace the header with crc message every 16 samples . [1:0] dclk_div dclk divide r . these bits c ontrol division of the dclk clock used to clock out conversion data on the doutx pins. the dclk signal is derived from the mclk applied to the ad7768 . the dclk divide mode allows the user to optimize the dclk output to fit th e application. optimizing the dclk per application depends on the requirements of the user. when the ad7768 are using the highest capacity output on the fewest doutx pins , for example, running in decimate by 32 using the dout0 and dout1 pins, the dclk must equal the mclk; thus, in this case , choosing the no division setting is the only way the user can output all the data within the conversion period. there are other cases , however , whe n the adc may be running in fast m ode with high decimation rates, or in median or eco mode where the dclk does not need to run at the same speed as mclk. in these cases , the dclk divide allows the user to reduce the clock speed and makes routing and isolating such signals easier. 0x0 rw 00 divide by 8 . 01 divide by 4 . 10 divide by 2 . 11 no division . digital filter ram built i n self test (bist) r egister address: 0x08, reset: 0x0, name: bist control table 46 . bit descriptions for b ist control bits bit name settings description reset access 0 ram_bist_start ram bist. filter ram bist is a built in self test of the internal ram. normal adc conversion is disrupted when this test is run. a synchronization pulse is required after this test is complete to resume normal adc operation. the test can be run at intervals depending on user preference. the status and result of the ram bist is available in the d evice status register ; see the ram_bist_pass and ram_bist_running bits in table 47. 0x0 rw 0 off . 1 begin ram bist .
data sheet ad7768/ad7768 - 4 rev. a | page 79 of 99 status register address: 0x09, reset: 0x0, name: device status table 47 . bit descriptions for device status bits bit name settings description reset access 3 chip_error chip error. chip error is a global error flag that is output within the s tatus byte of each a dc conversion output. the following bits lead to the c hip e rror bit being set to logic high: crc check on internally hard coded settings after power - up does not pass ; xor check on the internal m emory does not pass (t his check runs continuously in the backg round ); and c lock error is detected on power - up. 0x0 r 0 no error present . 1 error has occurred . 2 no_clock_error external clock c heck . this b it indicates whether the externally applied mclk is detected correctly. if the mclk is not applied cor rectly to the adc at power - up , this bit is set and the dclk frequency is approximately 16 mhz . if th is bit is set , the c hip e rror bit is set to logic high in the status bits of the data output headers , and the conversion results are output as all zeros reg ardless of the analog input voltages applied to the adc channels. 0x0 r 0 mclk detected . 1 no mclk detected . 1 ram_bist_pass bist p ass/ f ail. ram bist r esult s tatus. this bit indicates the result of the most recent ram bist. the result is latche d to this register and is only cleared by a device reset . 0x0 r 0 bist failed or not run . 1 bist passed . 0 ram_bist_running bist s tatus. reading back the value of this bit allows the user to poll when the bist test has finished. 0x0 r 0 bist not running . 1 bist running . revision identification regis ter address: 0x0a, reset: 0x 0 6 , name: revision id table 48 . bit descriptions for revision id bits bit name description reset access [7:0] revision_id asic revision. 8- bit id for revision details. 0x 06 r gp io control register address: 0x0e, reset: 0x00, name: gpio control table 49 . bit descriptions for gpio control bits bit name setting description reset access 7 ugpio_enable user gpio e nable. the gpio x pins are dual - purpose and can be operate d only when the device is in spi c ontrol mode . by default , when the ad7768 are powered u p in spi c ontrol mode , the gpio x pins are disabled. this bit is a universal enable/ disable for all gpio x input/outputs. the direction of each general - purpose pin is determined b y b its[4:0] of this register . 0x0 rw 0 gpio disabled . 1 gpio enabled . 4 gpioe4_filter gpio4 direction. this bit a ssigns the direction of gpio4 as either an input or an output. for spi control, gpio4 maps to p in 11 , which is the filter / gpio4 pin . 0x0 rw 0 input . 1 output .
ad7768/ad7768 - 4 data sheet rev. a | page 80 of 99 bits bit name setting description reset access 3 gpioe3_mode3 gpio3 direction . this bit a ssigns the direction of gpio 3 as either an input or a n output. for spi control , gpio3 maps to pin 15, which is the mode3/ gpio3 pin. 0x0 rw 0 input . 1 output . 2 gpi oe2_mode2 gpio2 direction . this bit assigns the direction of gpio 2 as either an input or an output. for spi control , gpio2 maps to p in 14 , which is the mode2/ gpio2 pin. 0x0 rw 0 input . 1 output . 1 gpioe1_mode1 gpio1 direction. this bit assigns the direction of gpio1 as either an input or an output. for spi control , gpio1 maps to p in 13 , which is the mode1/ gpio1 pin. 0x0 rw 0 input . 1 output . 0 gpio0_mode0 gpio0 direction. this bit assigns the direction of gpio0 as either an input or a n output. for spi control , gpio0 maps to p in 12 , which is the mode0/ gpio0 pin . 0x0 rw 0 input . 1 output . gpio write data regi ster address: 0x0f, reset: 0x00, name: gpio write data this register w rite s the values to be set on each of the gener al - purpose pins when selected as general - purpose outputs. each bit , from b it s[4: 0 ], maps directly to the gp iox pins . table 50 . bit descriptions for gpio write data bits bit name description reset access 4 gpio4_write gpio 4/ filter 0x 0 rw 3 gpio3_write gpio 3/ mode3 0x0 rw 2 gpio2_write gpio 2/ mode2 0x0 rw 1 gpio1_write gpio 1/ mode1 0x0 rw 0 gpio0_write gpio 0/ mode0 0x0 rw gpio read data regis ter address: 0x10, reset: 0x00, name: gpio read data this register r ead s back the value of th e logic input level at the general - purpose pins when selected to operate as general - purpose inputs. each bit, from bits[4:0], maps directly to the gp io0 to gpio4 pins . table 51 . bit descriptions for gpio read data bits bit name descri ption reset access 4 gpio4_read gpio4/ filter 0x0 r 3 gpio3_read gpio3/ mode3 0x0 r 2 gpio2_read gpio2/ mode2 0x0 r 1 gpio1_read gpio1/ mode1 0x0 r 0 gpio0_read gpio0/ mode0 0x00 r analog input precharge buffer enable regist er channel 0 to chan nel 3 add ress: 0x11, reset: 0x ff , name: precharge buffer 1 this register t urn s on or off the precharge buffer s on the analog inputs. when writing to these registers , the user must write the inverse of the required bit settings. for example, to clear b it 7 of this r egister , the user must write 0x01 to the register. this clear s b it 7 and set s all other bits. if the user reads the register again after writing 0x01, the data read is 0xfe, as required. table 52 . bit descriptions for precharge buffer 1 bits bit name settings description reset 7 ch3_prebuf_neg_en 0 off 0x 1 1 on
data sheet ad7768/ad7768 - 4 rev. a | page 81 of 99 bits bit name settings description reset 6 ch3_prebuf_pos_en 0 off 0x1 1 on 5 ch2_prebuf_neg_en 0 off 0x1 1 on 4 ch2_prebuf_pos_en 0 off 0x1 1 on 3 ch1_prebuf_neg_en 0 off 0x1 1 on 2 ch1_prebu f_pos_en 0 off 0x1 1 on 1 ch0_prebuf_neg_en 0 off 0x1 1 on 0 ch0_prebuf_pos_en 0 off 0x1 1 on analog input precharge buffer enable regist er channel 4 to chan nel 7 address: 0x12, reset: 0x ff , name: precharge buffer 2 this register turns on or off the precharge buffer s on the analog inputs. when writing to these registers, the user must write the inverse of the required bit settings. for example, to clear bit 7 of this register, the user must write 0x01 to the register. this clear s bit 7 and sets all other bits. if the user reads the register again after writing 0x01, the data read is 0xfe, as required. table 53 . bit descriptions for precharge buffer 2 bits bit name settings description reset 7 ch7_prebuf_neg_en 0 off 0x 1 1 on 6 ch7_prebuf_pos_en 0 off 0x1 1 on 5 ch6_prebuf_neg_en 0 off 0x1 1 on 4 ch6_prebuf_pos_en 0 off 0x1 1 on 3 ch5_prebuf_neg_en 0 off 0x1 1 on 2 ch5_prebuf_pos_en 0 off 0x1 1 on 1 ch4_prebuf_neg_en 0 off 0x1 1 on 0 ch 4_prebuf_pos_en 0 off 0x1 1 on positive reference p recharge buffer enable regist er address: 0x13, reset: 0x00, name: positive reference precharge buffer this register turns on or off the precharge buffer s on the reference positive input to each of th e adcs from channel 0 to channel 7. table 54 . bit descriptions for pos itive reference precharge buffer bits bit name settings description reset 7 ch7_refp_buf 0 off 0x0 1 on 6 ch6_refp_buf 0 off 0x0 1 on 5 ch5_refp_buf 0 o ff 0x0 1 on
ad7768/ad7768 - 4 data sheet rev. a | page 82 of 99 bits bit name settings description reset 4 ch4_refp_buf 0 off 0x0 1 on 3 ch3_refp_buf 0 off 0x0 1 on 2 ch2_refp_buf 0 off 0x0 1 on 1 ch1_refp_buf 0 off 0x0 1 on 0 ch0_refp_buf 0 off 0x0 1 on negative reference p recharge b uffer enable registe r address: 0x 14, reset: 0x00, name: negative reference precharge buffer this register turns on or off the precharge buffer s on the reference negative input to each of the adcs from channel 0 to channel 7. table 55 . bit descriptions for neg ative re ference precharge buffer bits bit name settings description reset 7 ch7_refn_buf 0 off 0x0 1 on 6 ch6_refn_buf 0 off 0x0 1 on 5 ch5_refn_buf 0 off 0x0 1 on 4 ch4_refn_buf 0 off 0x0 1 on 3 ch3_refn_buf 0 off 0x0 1 on 2 ch2_refn_bu f 0 off 0x0 1 on 1 ch1_refn_buf 0 off 0x0 1 on 0 ch0_refn_buf 0 off 0x0 1 on offset registers the chx_offset_msb, chx_offset_mid, and chx_offset_lsb registers are 24- bit, signed twos complement r egisters for channel offset adjustment. if th e channel gain setting is at its ideal nominal value of 0x555555, an lsb of offset register adjustme nt changes the digital output by ?4/3 lsbs. for example, changing the offset register from 0 to 100 changes the digital output by ?133 lsbs. as offset adjustment occurs before gain adjustment , the ratio of 4/3 changes linearly with gain adjustment via the chx_gain _x registers. after a reset or power cycle , the register values revert to the default factory setting. table 56 . per channel 24- bit offset registers, three 8- bit registers for e ach c h annel, split up as msb, mid, and lsb addre ss name description reset access msb mid lsb msb mid lsb 0x1e 0x1f 0x20 c hannel 0 o ffset channel 0 offset registers : upper, middle , and lower bytes (24 bits in total) 0x00 0x00 0x00 rw 0x21 0x22 0x23 channel 1 o ffset channel 1 offset registers: uppe r, middle , and lower bytes (24 bits in total) 0x00 0x00 0x00 rw 0x24 0x25 0x26 channel 2 o ffset channel 2 offset registers: upper, middle , and lower bytes (24 bits in total) 0x00 0x00 0x00 rw 0x27 0x28 0x29 channel 3 o ffset channel 3 offset registers : up per, middle , and lower bytes (24 bits in total) 0x00 0x00 0x00 rw 0x2a 0x2b 0x2c channel 4 o ffset channel 4 offset registers: upper, middle , and lower bytes (24 bits in total) 0x00 0x00 0x00 rw 0x2d 0x2e 0x2f channel 5 o ffset channel 5 offset registers: upper, middle , and lower bytes (24 bits in total) 0x00 0x00 0x00 rw 0x30 0x31 0x32 channel 6 o ffset channel 6 offset registers: upper, middle , and lower bytes (24 bits in total) 0x00 0x00 0x00 rw 0x33 0x34 0x35 channel 7 o ffset channel 7 offset regist ers: upper, middle , and lower bytes (24 bits in total) 0x00 0x00 0x00 rw
data sheet ad7768/ad7768 - 4 rev. a | page 83 of 99 gain registers each adc channel has an associated gain coefficient. the coefficient is stored in three single - byte registers split up as msb, mid, and lsb. each of the gain register s are factory programmed. nominally, this gain is around the value 0x555555 (for an adc channel). the user may overwrite the gain register setting however, after a reset or power cycle, the gain register values revert to the ha rd coded programmed factory s etting . table 57. per channel 24 - bit gain registers, 3 8 - bit registers for each channel, split up as msb, mid, and lsb address name description reset access msb mid lsb msb mid lsb 0x36 0x37 0x38 channel 0 g ain channel 0 g ain r egisters : upper, middle , and lower bytes (24 bits in total) 0xxx 0xxx 0xxx rw 0x39 0x3a 0x3b channel 1 g ain channel 1 g ain registers: upper, middle , and lower bytes (24 bits in total) 0xxx 0xxx 0xxx rw 0x3c 0x3d 0x3e channel 2 g ain channel 2 g ain registe rs: upper, middle , and lower bytes (24 bits in total) 0xxx 0xxx 0xxx rw 0x3f 0x40 0x41 channel 3 g ain channel 3 g ain registers: upper, middle , and lower bytes (24 bits in total) 0xxx 0xxx 0xxx rw 0x42 0x43 0x44 channel 4 g ain channel 4 g ain registers: up per, middle , and lower bytes (24 bits in total) 0xxx 0xxx 0xxx rw 0x45 0x46 0x47 channel 5 g ain channel 5 g ain registers: upper, middle , and lower bytes (24 bits in total) 0xxx 0xxx 0xxx rw 0x48 0x49 0x4a channel 6 g ain channel 6 g ain registers: upper, m iddle , and lower bytes (24 bits in total) 0xxx 0xxx 0xxx rw 0x4b 0x4c 0x4d channel 7 g ain channel 7 g ain registers: upper, middle , and lower bytes (24 bits in total) 0xxx 0xxx 0xxx rw sync phase offset re gisters the ad7768 ha ve one synchronization signal for all channels. the sync phase offset register allows the user to vary the phase delay on each of the channels relative to the synchronization edge received on the sync_in pin . see the sync phase offset adjustment section for details on the use of this function. table 58 . per channel 8 -b it sync p hase offset registers address name description reset access 0x4e channel 0 s ync o ffset channel 0 sync p hase offset register 0x00 rw 0x4f channel 1 s ync o ffset channel 1 sync phase offset register 0x00 rw 0x50 channel 2 s ync o ffset channel 2 sync phase offset register 0x00 rw 0x51 channel 3 s ync o ffset channel 3 sync phase offset register 0x00 rw 0x52 channel 4 s ync o ffset channel 4 sync phase offset register 0x00 rw 0x53 channel 5 s ync o ffset channel 5 sync phase offset register 0x00 rw 0x54 channel 6 s ync o ffset channel 6 sync phase offset register 0x00 rw 0x55 channel 7 s ync o ffset channel 7 sync phase offset register 0x00 rw adc diagnostic recei ve select register address: 0x56, reset: 0x00, name: diagnostic rx the ad7768 adc d iagnostic allows the user to select a zero - scale, positive full - scale , or negative full - scale input to the adc, which can be converted to verify the correct operation of the adc channel. this register enables the diagnostic. enable the receive (rx) for each channel and set each bit in this register to 1. the adc diagnostic feature depends on some features of the analog input precharge buffers. the user must ensure that the analog input precharge buffers are enabled on the channels that are selected to receive the diagnostic voltages internal ly . table 59 . bit descriptions for diagnostic rx bits bit name settings description rese t access 7 ch7_rx channel 7 0x0 rw 0 not in use 1 receive 6 ch6_rx channel 6 0x0 rw 0 not in use 1 receive 5 ch5_rx channel 5 0x0 rw 0 not in use 1 receive
ad7768/ad7768 - 4 data sheet rev. a | page 84 of 99 bits bit name settings description rese t access 4 ch4_rx channel 4 0x0 rw 0 not in use 1 receive 3 ch3_rx channel 3 0x0 rw 0 not in use 1 receive 2 ch2_rx channel 2 0x0 rw 0 not in use 1 receive 1 ch1_rx channel 1 0x0 rw 0 not in use 1 receive 0 ch0_rx channel 0 0x0 rw 0 not in use 1 receive adc diagnost ic control register address: 0x57, reset: 0x00, name: diagnostic mux control the ad7768 adc d iagnostic allows the user to select a zero - scale, positive full - scale , or negative full - scale input to the adc , which can be converted to verify the correct operation of the adc channel. this register controls the voltage th at is applied to each of the adc channels for the diagnostic. there are three input voltage options that the user can select . the voltage selected is mapped to the channel s based on which mode (mode a or mode b) they belong to, which is set according to th e c hannel m ode s elect register ( register 0x03). set b its [ 7 :0 ] to 1 in the adc d iagnostic r eceive s elect register, then select the voltage check desired for the channels on mode a and the c hannels on mode b through b its[2:0] and bits [6:4] , respectively. tab le 60 . bit descriptions for diagnostic mux control bits bit name settings description reset access [6:4] grpb_sel mux b. 0x0 rw 000 off . 011 positive full - scale adc check . a v oltage close to positive full scale is applied in ternally to the adc channel. 100 negative full - scale adc check . a v oltage close to negative (or minus) full scale is applied internally to the adc channel. 101 zero - scale adc check . a voltage close to 0 v is applied internally to the adc channel. [2:0] grpa_sel mux a. 0x0 rw 000 off . 011 positive full - scale adc check . a v oltage close to positive full scale is applied internally to the adc channel. 100 negative full - scale adc check . a v oltage close to negative (or minus) full scale is applied internally to the adc channel. 101 zero - scale adc check . a voltage close to 0 v is applied internally to the adc channel.
data sheet ad7768/ad7768 - 4 rev. a | page 85 of 99 modulator delay cont rol register address: 0x58, reset: 0x02 , name: modulator delay control table 61 . bit descriptions for modulator delay control bits bit name settings description reset access [3:2] clk_mod_del_en enable delayed modulator clock . 0x0 rw 00 d isabled delayed clock for all channels . 01 e nable delayed clock for c hannel 0 to channel 3 only on the ad7768 . 10 e nable delayed cl ock for channel 4 to channel 7 only on ad7768 . 11 e nabl e delayed clock for all channels . [1:0] reserved 10 not a user option. must be set to 0x2. 0x2 rw chopping control reg ister address: 0x59, reset: 0x0a, name: chop control table 62 . bit descriptions for chop c ontrol bits bit name settings description reset access [3:2] grpa_chop group a c ho pping 0x2 rw 01 chop at f mod /8 10 chop at f mod /32 [1:0] grpb_chop group b c hopping 0x2 rw 01 chop at f mod /8 10 chop at f mod /32
ad7768/ad7768 - 4 data sheet rev. a | page 86 of 99 ad7768 - 4 register map details (spi control) ad7768 -4 register map table 63 . detailed ad7768 -4 register map reg. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x00 channel standby unused ch_3 ch_2 ch_1 ch_0 0x00 rw 0x01 channel mode a unused filter_type_a dec_rate_a 0x0d rw 0x02 channel mode b unused filter_type_b dec_rate_b 0x0d rw 0x03 channel mode select reserved ch_3_mode ch_2_mode reserved ch_1_mode ch_0_mode 0x00 rw 0x04 power_mode sleep_mode unused power_mode lvds_enable unused mclk_div 0x00 rw 0x05 general c onfiguration unused reserved reti me_en vcm_pd reserved unused vcm_vsel 0x08 rw 0x06 data c ontrol spi_sync unused single_shot_en unused spi_reset 0x80 rw 0x07 interface c onfiguration unused crc_select dclk_div 0x0 rw 0x08 bist c ontrol unused ram_bist_ start 0x0 rw 0x09 device s tatus un used chip_error no_clock_ error ram_bist_pass ram_bist_ running 0x0 r 0x0a revision id revision_id 0x06 r 0x0b reserved reserved 0x00 r 0x0c reserved reserved 0x00 r 0x0d reserved reserved 0x00 r 0x0e gpio c ontrol ugpio_ enable unused gpioe4_filter gp ioe3_mode3 gpioe2_mode2 gpioe1_mode1 gpio0_mode0 0x00 rw 0x0f gpio write data unused gpio4_write gpio3_write gpio2_write gpio1_write gpio0_write 0x00 rw 0x10 gpio read data unused gpio4_read gpio3_read gpio2_read gpio1_read gpio0_read 0x00 r 0x11 precha rge buffer 1 reserved ch1_prebuf_ neg_en ch1_prebuf_ pos_en ch0_prebuf_ neg_en ch0_prebuf_ pos_en 0xff rw 0x12 precharge buffer 2 reserved ch3_prebuf_ neg_en ch3_prebuf_ pos_en ch2_prebuf_n e g_en ch2_prebuf_ pos_en 0xff rw 0x13 positive reference precharg e buffer reserved ch3_refp_ buf ch2_refp_buf reserved ch1_refp_buf ch0_refp_ buf 0x00 rw 0x14 negative reference precharge buff er reserved ch3_refn_ buf ch2_refn_buf reserved ch1_refn_buf ch0_refn_ buf 0x00 rw 0x1e channel 0 o ffset ch0_offset_msb 0x00 rw 0x1f ch0_offset_mid 0x20 ch0_offset_lsb 0x21 channel 1 o ffset ch1_offset_msb 0x00 rw 0x22 ch1_offset_mid 0x23 ch1_offset_lsb 0x24 reserved reserved 0x00 rw 0x25 reserved 0x26 reserved 0x27 reserved reserved 0x00 rw 0x28 reser ved 0x29 reserved 0x2a channel 2 o ffset ch2_offset_msb 0x00 rw 0x2b ch2_offset_mid 0x2c ch2_offset_lsb 0x2d channel 3 o ffset ch3_offset_msb 0x00 rw 0x2e ch3_offset_mid 0x2f ch3_offset_lsb 0x30 reserved reserved 0x00 rw 0x31 reser ved 0x32 reserved 0x33 reserved reserved 0x00 rw 0x34 reserved 0x35 reserved 0x36 channel 0 g ain ch0_gain_msb 0xxx rw 0x37 ch0_gain_mid 0x38 ch0_gain_lsb
data sheet ad7768/ad7768 - 4 rev. a | page 87 of 99 reg. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x39 channel 1 g ain ch1_gain_msb 0xxx rw 0x3a ch1_gain_mid 0x3b ch1_gai n_lsb 0x3c reserved reserved 0xxx rw 0x3d reserved 0x3e reserved 0x3f reserved reserved 0xxx rw 0x40 reserved 0x41 reserved 0x42 channel 2 g ain ch2_gain_msb 0xxx rw 0x43 ch2_gain_mid 0x44 ch2_gain_lsb 0x45 channel 3 g ain ch3_g ain_msb 0xxx rw 0x46 ch3_gain_mid 0x47 ch3_gain_lsb 0x48 reserved reserved 0xxx rw 0x49 reserved 0x4a reserved 0x4b reserved reserved 0xxx rw 0x4c reserved 0x4d reserved 0x4e channel 0 sync offset ch0_sync_offset 0x00 rw 0x4f ch annel 1 sync offset ch1_sync_offset 0x00 rw 0x50 reserved reserved 0x00 rw 0x51 reserved reserved 0x00 rw 0x52 channel 2 sync offset ch2_sync_offset 0x00 rw 0x53 channel 3 sync offset ch3_sync_offset 0x00 rw 0x54 reserved reserved 0x00 rw 0x55 reserv ed reserved 0x00 rw 0x56 diagnostic rx reserved ch3_rx ch2_rx reserved ch1_rx ch0_rx 0x00 rw 0x57 diagnostic mux control unused grpb_sel unused grpa_sel 0x00 rw 0x58 modulator delay control unused clk_mod_del_en reserved 0x02 rw 0x59 chop c ontrol unuse d grpa_chop grpb_chop 0x0a rw
ad7768/ad7768 - 4 data sheet rev. a | page 88 of 99 channel standby regi ster address: 0x00, reset: 0x00, name: channel standby each of the adc channels can be put into standby mode independently by setting the appropriate bit in the channel standby reg ister. when a channel is in standby mode, its position in the data output stream is held. the 8 - bit header is all zeros, as is the conversion result output of 24 zeros. the vcm voltage output is associated with the channel 0 circuitry. if channel 0 is put into standby mode, the v cm voltage output is also disabled for maximum power savings. channel 0 must be enabled while vcm is being used externally to the ad7768 - 4 . the crystal excitation circuitry is associated with the channel 2 circuitry. if channel 2 is put into standby mode, the crystal circuitry is also disabled for maximum power savings. channel 2 must be enabled while the external crystal is used on the ad7768 - 4 . table 64 . bit descriptions for channel standby bits bit name settings description reset access 3 ch_3 channel 3 0x0 rw 0 enabled 1 standby 2 ch_2 channel 2 0x0 rw 0 enabled 1 standby 1 ch_1 channel 1 0x0 rw 0 enabled 1 standby 0 ch_0 channel 0 0x0 rw 0 enabled 1 standby channel mode a regis ter address: 0x01, reset: 0x0d, name: channel mode a two mode options are available on the ad7768 - 4 adcs. the channel modes are defined by the contents of the channel mode a and channel mode b registers. each mode is then mapped as desired to the required adc channel. mode a and mode b allow different filt er types and decimation rates to be selected and mapped to any of the adc channels. when different decimation rates are selected, the ad7768 - 4 output a data ready signal at the fastest s elected decimation rate. any channel that runs at a lower output data rate is updated only at that slower rate. in between valid result data, the data for that ch annel is set to zero and the repeated data bit is set in the header status bits to distinguish it from a real conversion result (see the adc conversion output: header and data section). table 65 . bit descriptions for channel mode a bits bit name settings description reset access 3 fil ter_type_a filter selection 0x1 rw 0 wideband filter 1 sinc5 filter [2:0] dec_rate_a decimation rate selection 0x5 rw 000 32 001 64 010 128 011 256 100 512 101 1024 110 1024 111 1024
data sheet ad7768/ad7768 - 4 rev. a | page 89 of 99 channel mo de b register address: 0x02, reset: 0x0d, name: channel mode b table 66 . bit descriptions for channel mode b bits bit name settings description reset access 3 filter_type_b filter selection 0x1 rw 0 wideband filter 1 sinc5 filter [2:0] dec_rate_b decimation rate selection 0x5 rw 000 32 001 64 010 128 011 256 100 512 101 1024 110 1024 111 1024 channel mode select register address: 0x03, reset: 0x00, name: channel mod e select this register selects the mapping of each adc channel to either channel mode a or channel mode b. table 67 . bit descriptions for channel mode select bits bit name settings description reset access 5 ch_3_mode channel 3 0x0 rw 0 mode a 1 mode b 4 ch_2_mode channel 2 0x0 rw 0 mode a 1 mode b 1 ch_1_mode channel 1 0x0 rw 0 mode a 1 mode b 0 ch_0_mode channel 0 0x0 rw 0 mode a 1 mode b power mode select re gister address: 0x04, rese t: 0x00, name: power_mode table 68 . bit descriptions for power_mode bits bit name settings description reset access 7 sleep_mode in sleep mode, many of the digital clocks are disabled and all of the adcs are disabled . the analog ldo s are not disabled. 0x0 rw the ad7768 -4 spi is live and is available to the user. writing to this bit brings the ad7768 -4 out of sleep mode again. 0 normal operation. 1 sleep mode.
ad7768/ad7768 - 4 data sheet rev. a | page 90 of 99 bits bit name settings description reset access [5:4] power_mode power mode. the power mode bits control the power mode setting for the bias currents used on all adcs on the ad7768 -4 . the user can select the current consumption target to meet the application. the power modes of fast, median, and eco give optimum performance when mapped to the correct mclk division setting. these power mode bits do not c ontrol the mclk division of the adcs. see the mclk_div bits for control of the division of the mclk input. 0x0 rw 00 eco. 10 median. 11 fast. 3 lvds_enable lvds clock. 0x0 rw 0 lvds input clock disabled. 1 lvds input clock enabled. [1:0] mclk_div mclk division. the mclk division bits control the divided ratio between the mclk applied at the input to the ad7768 -4 and the clock used by each of the adc modulators. the appropriate division ratio depends on the following factors: power mode, decimation rate, and the base mclk available in the system. see the clocking, sampling tree, and power scaling section for more information on setting mclk_div correctly. 0x0 rw 00 mclk/32: with a base mclk of 32.768 mhz, set to mclk/32 for eco mode. 10 mclk/8: with a base mclk of 32.768 mhz, set to mclk/8 for median mode. 11 mclk/4: with a base mclk of 32.768 mhz, set to mclk/4 for fast mode. general device confi guration register address: 0x05, reset: 0x08, name: general configuration table 69 . bit descriptions for general configuration bits bit name settings description reset access 5 retime_en sync_out signal retime enable bit. 0x0 rw 0 disabled: n ormal timing of sync_out . 1 e nabled: sync_out signal derived from alternate mclk edge. 4 vcm_pd vcm buffer power - down. 0x0 rw 0 enabled: vcm buffer normal mode. 1 powered down: vcm buffer powered down. 3 reserved 1 not a user option. this bit must be s et to 1. 0x1 rw 1:0 vcm_vsel vcm voltage. these bits select the output voltage of the vcm pin. this voltage is derived from the avdd1 supply and can be output as half of that avdd1 voltage, or other fixed voltages, with respect to avss. the vcm voltag e output is associated with the channel 0 circuitry. if channel 0 is put into standby mode, the vcm voltage output is also disabled for maximum power savings. channel 0 must be enabled while vcm is being used externally to the ad7768 -4. 0x0 rw 00 (avdd1 ? avss)/2 v. 01 1.65 v. 10 2.5 v. 11 2.14 v.
data sheet ad7768/ad7768 - 4 rev. a | page 91 of 99 data control: soft r eset, sync, and sing le - shot control registe r address: 0x06, reset: 0x80, name: data control tab le 70 . bit descriptions for data control bits bit name settings description reset access 7 spi_sync software synchronization of the ad7768 -4 . this command has the same effect as sending a signal pulse to the start pin. to operate the spi_sync , the user must write to this bit two separate times. first, write a zero, putting spi_sync low, and then write a 1 to set spi_sync logic high again. the spi_ sync command is recognized after the last rising edge of sclk in the spi instruction where the spi_sync bit is changed from low to high. the spi_sync command is then output synchronous to the ad7768 -4 mclk on the sync_out pin. the user must connect the sync_out signal to the sync_in pin on the pcb. the sync_out pin can also be routed to the sync_in p ins of other ad7768 -4 devices, allowing larger channel count simultaneous sampling systems. as per any synchronizatio n pulse seen by the sync_in pin, the digital filter s of the ad7768 -4 are reset. the full settling time of the filters must elapse before data is output on the data interface. in a daisy - chained system of ad7768 -4 devices, two successive synchronization pulses must be applied to guarantee that all adcs are synchronized. two synchronization pulses are also required in a system of more than one ad7768 -4 device sharing a single mclk signal, where the drdy pin of only one device is used to detect new data. 0x1 rw 0 change to spi_sync low. 1 change to spi_sync high. 4 single_shot _en one - shot mode. enables one - shot mode. in one - shot mode, the ad7768 -4 output a conversion result in response to a sync_in rising edge. 0x0 rw 0 disabled. 1 enabled. [1:0] spi_reset soft reset. these bits allow a full device reset over the spi port. two successive commands must be received in the correct order to generate a reset: first, write 0x03 to the soft reset register, and then write 0x02 to the sof t reset register. this sequence causes the digital core to reset and all registers return to their default values. following a soft reset, if the spi master sends a command to the ad7768 -4 , the devices respond on the next frame to that command with an output of 0x0e00. 0x0 rw 00 no effect. 01 no effect. 10 second reset command. 11 first reset command. interface configurat ion register address: 0x07, reset: 0x0, name: interface configuration table 71 . bit descriptions for interface configuration bits bit name settings description reset access [3:2] crc_select crc select. these bits allow the user to implement a crc on the data interface. when se lected, the crc replaces the header every fourth or 16 th output sample depending on the crc option chosen. there are two options for the crc; both use the same polynomial: x 8 + x 2 + x + 1. the options offer the user the ability to reduce the duty cycle of the crc calculation by performing it less often: in the case of having it every 16 th sample or more often in the case of every fourth conversion. the crc is calculated on a per channel basis and it includes conversion data only. 0x0 rw 00 no crc. statu s bits with every conversion. 01 replace the header with crc message every 4 samples. 10 replace the header with crc message every 16 samples. 11 replace the header with crc message every 16 samples.
ad7768/ad7768 - 4 data sheet rev. a | page 92 of 99 bits bit name settings description reset access [1:0] dclk_div dclk divider. these bi ts control division of the dclk clock used to clock out conversion data on the doutx pins. the dclk signal is derived from the mclk applied to the ad7768 -4 . the dclk divide mode allows t he user to optimize the dclk output to fit the application. optimizing the dclk per application depends on the requirements of the user. when the ad7768 -4 are using the highest capacity output on the fewest doutx pins, for example, running in decimate by 32 using the dout0 and dout1 pins, the dclk must equal the mclk; thus, in this case, choosing the no division setting is the only way the user can output all the data within the conversio n period. there are other cases, however, when the adc may be running in fast mode with high decimation rates, or in median or eco mode where the dclk does not need to run at the same speed as mclk. in these cases, the dclk divide allows the user to reduce the clock speed and makes routing and isolating such signals easier. 0x0 rw 00 divide by 8. 01 divide by 4. 10 divide by 2. 11 no division. digital filter ram b uilt i n self test (bist) r egister address: 0x08, reset: 0x0, name: bist control table 72 . bit descriptions for bist control bits bit name settings description reset access 0 ram_bist_start ram bist. filter ram bist is a built in self test of the ram storage of the coefficients used by the digital filte r. normal adc conversion is disrupted when this test is run. a synchronization pulse is required after this test is complete to resume normal adc operation. the test can be run at intervals depending on user preference. the status and result of the ram bis t is available in the device status register; see the ram_bist_pass and ram_bist_running bits in table 73. 0x0 rw 0 off. 1 begin ram bist. status register address: 0x09, reset: 0x0, name: device status table 73 . bit descriptions for device status bits bit name settings description reset access 3 chip_error chip error. chip error is a global error flag that is output within the status byte of each adc conversion output. the followi ng bits lead to the chip error bit being set to logic high: crc check on internally hard coded settings after power - up does not pass; xor check on the memory map does not pass (this check runs continuously in the background); and clock error is detected on power - up. 0x0 r 0 no error present. 1 error has occurred. 2 no_clock_error external clock check. this bit indicates whether the externally applied mclk is detected correctly. if the mclk is not applied correctly to the adc at power - up, this bi t is set and the dclk frequency is approximately 16 mhz . if this bit is set, the chip error bit is set to logic high in the status bits of the data output headers, and the conversion results are output as all zeros regardless of the analog input voltages a pplied to the adc channels. 0x0 r 0 mclk detected. 1 no mclk detected.
data sheet ad7768/ad7768 - 4 rev. a | page 93 of 99 bits bit name settings description reset access 1 ram_bist_pass bist pass/fail. ram bist result status. this bit indicates the result of the most recent ram bist. the result is latched to this register and is only cleared by a device reset. 0x0 r 0 bist failed or not run. 1 bist passed. 0 ram_bist_running bist status. reading back the value of this bit allows the user to poll when the bist test has finished. 0x0 r 0 bist not running. 1 bist running. revision identificat ion register address: 0x0a, reset: 0x06, name: revision id table 74 . bit descriptions for revision id bits bit name description reset access [7:0] revision_id asic revision. 8 - bit id for revision details. 0x06 r gpio control registe r address: 0x0e, reset: 0x00, name: gpio control table 75 . bit descriptions for gpio control bits bit name setting description reset access 7 ugpio_enable user gpio enable. the gpiox pins are dual - purpose and c an be operated only when the device is in spi control mode. by default, when the ad7768 -4 are powered u p in spi control mode, the gpiox pins are disabled. this bit is a universal enable/ disable for all gpiox input/outputs. the direction of each general - purpose pin is determined by bits[4:0] of this register. 0x0 rw 0 gpio disabled. 1 gpio enabled. 4 gpioe4_filter gpio4 direction. this bit assigns the direction of gpio4 as eit her an input or an output. for spi control, gpio4 maps to pin 11, which is the filter /gpio4 pin. 0x0 rw 0 input. 1 output. 3 gpioe3_mode3 gpio3 direction. this bit assigns the direction of gpio3 as either an input or a n output. for spi control, gpio3 maps to pin 15, which is the mode3/ gpio3 pin. 0x0 rw 0 input. 1 output. 2 gpioe2_mode2 gpio2 direction. this bit assigns the direction of gpio2 as either an input or an output. for spi control, gpio2 maps to pin 14, which is the mode2/ gp io2 pin. 0x0 rw 0 input. 1 output. 1 gpioe1_mode1 gpio1 direction. this bit assigns the direction of gpio1 as either an input or an output. for spi control, gpio1 maps to pin 13, which is the mode1/ gpio1 pin. 0x0 rw 0 input. 1 output. 0 gpio0_mode0 gpio0 direction. this bit assigns the direction of gpio0 as either an input or a n output. for spi control, gpio0 maps to pin 12, which is the mode0/ gpio0 pin . 0x0 rw 0 input. 1 output.
ad7768/ad7768 - 4 data sheet rev. a | page 94 of 99 gpio write data regi ster address: 0x0f, reset: 0x00, name: gpio write data this register writes the values to be set on each of the general - purpose pins when selected as general - purpose outputs. each bit, from bits[4:0], maps directly to the gpiox pins. table 76 . bit descri ptions for gpio write data bits bit name description reset access 4 gpio4_write gpio4/ filter 0x0 rw 3 gpio3_write gpio3/ mode3 0x0 rw 2 gpio2_write gpio2/ mode2 0x0 rw 1 gpio1_write gpio1/ mode1 0x0 rw 0 gpio0_write gpio0/ mode0 0x0 rw gpio read data r egister address: 0x10, reset: 0x00, name: gpio read data this register reads back the value of the logic input level at the general - purpose pins when selected to operate as general - purpose inputs. each bit, from bits[4:0], maps directly to the gpio0 to gpi o4 pins. table 77 . bit descriptions for gpio read data bits bit name description reset access 4 gpio4_read gpio4/ filter 0x0 r 3 gpio3_read gpio3/ mode3 0x0 r 2 gpio2_read gpio2/ mode2 0x0 r 1 gpio1_read gpio1/ mode1 0x0 r 0 gpio0_re ad gpio0/ mode0 0x00 r analog input prechar ge buf fer enable register channel 0 and channel 1 address: 0x11, reset: 0xff, name: precharge buffer 1 this register turns on or off the precharge buffers on the analog inputs. when writing to these registers, t he user must write the inverse of the required bit settings. for example, to clear bit 7 of this register, the user must write 0x01 to the register. this clear s bit 7 and sets all other bits. if the user reads the register again after writing 0x01, the dat a read is 0xfe, as required. table 78 . bit descriptions for precharge buffer 1 bits bit name settings description reset 3 ch1_prebuf_neg_en 0 off 0x1 1 on 2 ch1_prebuf_pos_en 0 off 0x1 1 on 1 ch0_prebuf_neg_en 0 off 0x1 1 on 0 ch0_prebuf_pos_en 0 off 0x1 1 on
data sheet ad7768/ad7768 - 4 rev. a | page 95 of 99 analog input prechar ge buffer enable regist er channel 2 and channel 3 address: 0x12, reset: 0xff, name: precharge buffer 2 this register turns on or off the precharge buffers on the analog inputs. when writing to these registers, the user must write the inverse of the required bit settings. for example, to clear bit 7 of this register, the user must write 0x01 to the register. this clear s bit 7 and sets all other bits. if the user reads the register agai n after writing 0x01, the data read is 0xfe, as required. table 79 . bit descriptions for precharge buffer 2 bits bit name settings description reset 3 ch3_prebuf_neg_en 0 off 0x1 1 on 2 ch3_prebuf_pos_en 0 off 0x1 1 on 1 ch 2_prebuf_neg_en 0 off 0x1 1 on 0 ch2_prebuf_pos_en 0 off 0x1 1 on positive reference p recharge buffer enab le register address: 0x13, reset: 0x00, name: positive reference precharge buffer this register turns on or off the precharge buffers on th e reference positive input to each of the adcs from channel 0 to channel 3 . table 80 . bit descriptions for positive reference precharge buffer bits bit name settings description reset 5 ch3_refp_buf 0 off 0x0 1 on 4 ch2_refp_bu f 0 off 0x0 1 on 1 ch1_refp_buf 0 off 0x0 1 on 0 ch0_refp_buf 0 off 0x0 1 on negative reference p recharge buffer enab le register address: 0x14, reset: 0x00, name: negative reference precharge buffer this register turns on or off the prechar ge buffers on the reference negative input to each of the adcs from channel 0 to chan nel 3 . table 81 . bit descriptions for negative reference precharge buffer bits bit name settings description reset 5 ch3_refn_buf 0 off 0x0 1 on 4 ch2_refn_buf 0 off 0x0 1 on 1 ch1_refn_buf 0 off 0x0 1 on 0 ch0_refn_buf 0 off 0x0 1 on
ad7768/ad7768 - 4 data sheet rev. a | page 96 of 99 offset registers the chx_offset_msb, chx_offset_mid, and chx_offset_lsb registers are 24 - bit, signed twos complement r egisters for channel offse t adjustment. if the channel gain setting is at its ideal nominal value of 0x555555, an lsb of offset register adjustment changes the digital output by ?4/3 lsbs. for example, changing the offset register from 0 to 100 changes the digital output by ?133 lsbs. as offset adjustment occurs before gain adjustment, the ratio of 4/3 changes linearly with gain adjustment via the chx_gain_x registers. after a reset or power cycle, the register values revert to the default factory setting. table 82 . per channel 24- bit offset registers, three 8 - bit registers for each channel, split up as msb, mid, and ls b address name description reset access msb mid lsb msb mid lsb 0x1e 0x1f 0x20 channel 0 o ffset channel 0 offset registers: upper, middle, and lower bytes (24 bits in total) 0x00 0x00 0x00 rw 0x21 0x22 0x23 channel 1 o ffset channel 1 offset registe rs: upper, middle, and lower bytes (24 bits in total) 0x00 0x00 0x00 rw 0x2a 0x2b 0x2c channel 2 o ffset channel 2 offset registers: upper, middle, and lower bytes (24 bits in total) 0x00 0x00 0x00 rw 0x2d 0x2e 0x2f channel 3 o ffset channel 3 offset regis ters: upper, middle, and lower bytes (24 bits in total) 0x00 0x00 0x00 rw gain registers each adc channel has an associated gain coefficient. the coefficient is stored in three single - byte registers split up as msb, mid, and lsb. each of the gain registe rs are factory programmed. nominally, this gain is around the value 0x555555 (for an adc channel). the user may overwrite the gain register setting however, after a reset or power cycle, the gain register values revert to the ha rd coded programmed factory setting. table 83. per channel 24 - bit gain registers, 3 8 - bit registers for each channel, split up as msb, mid, and lsb address name description reset access msb mid lsb msb mid lsb 0x36 0x37 0x38 channel 0 g ain channel 0 gain registers: upper, middle, and lower bytes (24 bits in total) 0xxx 0xxx 0xxx rw 0x39 0x3a 0x3b channel 1 g ain channel 1 gain registers: upper, middle, and lower bytes (24 bits in total) 0xxx 0xxx 0xxx rw 0x42 0x43 0x44 channel 2 g ain channel 2 gain regist ers: upper, middle, and lower bytes (24 bits in total) 0xxx 0xxx 0xxx rw 0x45 0x46 0x47 channel 3 g ain channel 3 gain registers: upper, middle, and lower bytes (24 bits in total) 0xxx 0xxx 0xxx rw sync phase offset re gisters the ad7768 - 4 have one synchronization signal for all channels. the sync phase offset register allows the user to vary the phase delay on each of the channels relative to the synchronization edge received on the sync_in pin . see the sync phase offset adjustment section for details on the use of this function. table 84 . per channel 8 - bit sync phase offset registers address name description reset access 0x4e channel 0 sync offset channel 0 sync phase offset register 0x00 rw 0x4f channel 1 sync offset channel 1 sync phase offset register 0x00 rw 0x52 channel 2 sync offset channel 2 sync phase offset register 0x00 rw 0x53 channel 3 sync offset channel 3 sync phase offset register 0x00 rw adc diagnostic recei ve select register address: 0x56, reset: 0x00, name: diagnostic rx the ad7768 - 4 adc diagnostic allows the use r to select a zero - scale, positive full - scale, or negative full - scale input to the adc, which can be converted to verify the correct operation of the adc channel. this register enables the diagnostic. enable the receive (rx) for each channel and set each b it in this register to 1. the adc diagnostic feature depends on some features of the analog input precharge buffers. the user must ensure that the anal og input precharge buffers are enabled on the channels that are selected to receive the diagnostic voltag es internally. table 85 . bit descriptions for diagnostic rx bits bit name settings description reset access 5 ch3_rx channel 3 0x0 rw 0 not in use 1 receive
data sheet ad7768/ad7768 - 4 rev. a | page 97 of 99 bits bit name settings description reset access 4 ch2_rx channel 2 0x0 rw 0 not in use 1 receive 1 c h1_rx channel 1 0x0 rw 0 not in use 1 receive 0 ch0_rx channel 0 0x0 rw 0 not in use 1 receive adc diagnostic contr ol register address: 0x57, reset: 0x00, name: diagnostic mux control the ad7768 - 4 adc diagnostic allows the user to select a zero - scale, positive full - scale, or negative full - scale input to the adc, which can be converted to verify the correct operation of the adc channel. this register controls the voltage that is applied to each of the adc channels for the diagnostic. there are three input voltage options that the user can select. the voltage selected is mapped t o the channel s based on which mode (mode a or mode b) they belong to, which is set accor ding to the channel mode select register (register 0x03). set bits[7:0] to 1 in the adc diagnostic receive select register, then select the voltage check desired for the channels on m ode a and the channels on mode b through bits[2:0] and bits[6:4], respect ively. table 86 . bit descriptions for diagnostic mux control bits bit name settings description reset access 6:4 grpb_sel mux b. 0x0 rw 000 off. 011 positive full - scale adc check. a voltage close to positive full scale is applied internally to the adc channel. 100 negative full - scale adc check. a voltage close to negative (or minus) full scale is applied internally to the adc channel. 101 ero - scale adc check. a voltage close to 0 v is applied internally to the ad c channel. 2:0 grpa_sel mux a. 0x0 rw 000 off. 011 positive full - scale adc check. a voltage close to positive full scale is applied internally to the adc channel. 100 negative full - scale adc check. a voltage close to negative (or minus) full scale is applied internally to the adc channel. 101 ero - scale adc check. a voltage close to 0 v is applied internally to the adc channel. modulator delay cont rol register address: 0x58, reset: 0x02, name: modulator delay control table 87 . bit descriptions for modulator delay control bits bit name settings description reset access [3:2] clk_mod_del_en enable delayed modulator clock. 0x0 rw 00 disabled delayed clock for all channels. 01 enable delayed clock for c hannel 0 and channel 1 only on the ad7768 -4. 10 enable delayed clock for channel 2 and channel 3 only on the ad7768 -4. 11 enable delayed clock for all channels. [1:0] reserved 10 not a user option. must be set to 0x2. 0x2 rw
ad7768/ad7768 - 4 data sheet rev. a | page 98 of 99 chopping control reg ister address: 0x59, reset: 0x0a, name: chop control table 88 . bit descriptions for cho p control bits bit name settings description reset access [3:2] grpa_chop group a chopping 0x2 rw 01 chop at f mod /8 10 chop at f mod /32 [1:0] grpb_chop group b chopping 0x2 rw 01 chop at f mod /8 10 chop at f mod /32
data sheet ad7768/ad7768 - 4 rev. a | page 99 of 99 outline dimensions compliant t o jedec s t andards ms-026-bcd 051706- a t op view (pins down) 1 16 17 33 32 48 49 64 0.27 0.22 0.17 0.50 bsc lead pitch 12.20 12.00 sq 1 1.80 pin 1 1.60 max 0.75 0.60 0.45 10.20 10.00 sq 9.80 view a 0.20 0.09 1.45 1.40 1.35 0.08 coplanarit y view a ro ta ted 90 ccw se a ting plane 0.15 0.05 7 3.5 0 figure 110 . 64 - lead low profile quad flat package [lqfp] (st - 64- 2) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ad7768bstz ?40c to +105c 64- lead low profile quad flat package [lqfp] st -64-2 ad7768bstz - rl7 ?40c to +105c 64 - lead low profile quad flat package [lqfp] st - 64 - 2 ad7768bstz -rl ?40c to +105c 64- lead low profile quad flat package [lqfp] st -64-2 ad7768 - 4bstz ?40 c to +105c 64- lead low profile quad flat package [lqfp] st -64-2 ad7768 - 4bstz - rl7 ?40c to +105c 64- lead low profile quad flat package [lqfp] st -64-2 ad7768 - 4bstz - rl ?40c to +105c 64- lead low profile quad flat package [lqfp] st -64-2 eval - ad7768fmcz evaluation board eval - ad7768 - 4fmcz ad7768 - 4 evaluation board eval - sdp - ch1z controller board 1 z = rohs compliant part . ? 2016 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d14001 - 0- 3/16(a)

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